| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSubtargetInfo.cpp | 54 return getSchedModel().PostRAScheduler;
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| H A D | TargetSchedule.cpp | 65 SchedModel = TSInfo->getSchedModel();
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| H A D | MachineCombiner.cpp | 648 SchedModel = STI->getSchedModel();
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| H A D | MachinePipeliner.cpp | 932 if (STI && STI->getSchedModel().hasInstrSchedModel()) {
934 STI->getSchedModel().getSchedClassDesc(SchedClass);
946 STI->getSchedModel().getProcResource(PRE.ProcResourceIdx);
975 if (STI && STI->getSchedModel().hasInstrSchedModel()) {
977 STI->getSchedModel().getSchedClassDesc(SchedClass);
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| /freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
| H A D | RegisterFileStatistics.cpp | 22 const MCSchedModel &SM = STI.getSchedModel();
118 assert(STI.getSchedModel().hasExtraProcessorInfo() &&
121 STI.getSchedModel().getExtraProcessorInfo();
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| H A D | SchedulerStatistics.cpp | 22 : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0),
25 Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) {
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| H A D | ResourcePressureView.cpp | 27 const MCSchedModel &SM = STI.getSchedModel();
108 const MCSchedModel &SM = STI.getSchedModel();
151 printColumnNames(FOS, STI.getSchedModel());
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| H A D | InstructionInfoView.cpp | 23 const MCSchedModel &SM = STI.getSchedModel();
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| H A D | TimelineView.cpp | 46 const MCSchedModel &SM = STI.getSchedModel();
167 CumulativeExecutions, STI.getSchedModel().MicroOpBufferSize);
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| H A D | BottleneckAnalysis.cpp | 454 : STI(sti), MCIP(Printer), Tracker(STI.getSchedModel()), DG(S.size() * 3),
620 const MCSchedModel &SM = STI.getSchedModel();
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | Context.cpp | 32 const MCSchedModel &SM = STI.getSchedModel();
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| H A D | InstrBuilder.cpp | 33 const MCSchedModel &SM = STI.getSchedModel();
35 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
42 const MCSchedModel &SM = STI.getSchedModel();
250 const MCSchedModel &SM = STI.getSchedModel();
510 assert(STI.getSchedModel().hasInstrSchedModel() &&
516 const MCSchedModel &SM = STI.getSchedModel();
623 unsigned ProcID = STI.getSchedModel().getProcessorID();
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSchedule.cpp | 91 const MCSchedModel &SM = STI.getSchedModel();
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| H A D | MCSubtargetInfo.cpp | 315 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/Stages/ |
| H A D | DispatchStage.cpp | 35 DispatchWidth = Subtarget.getSchedModel().IssueWidth;
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 156 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } function in class:llvm::MCSubtargetInfo
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| /freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-mca/ |
| H A D | llvm-mca.cpp | 334 if (!PrintInstructionTables && !STI->getSchedModel().isOutOfOrder()) {
340 if (!STI->getSchedModel().hasInstrSchedModel()) {
346 if (STI->getSchedModel().InstrItineraries)
427 const MCSchedModel &SM = STI->getSchedModel();
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.cpp | 255 SchedModel = DAG->getSchedModel();
262 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries();
272 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
273 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 262 const TargetSchedModel *getSchedModel() const { return &SchedModel; } function in class:llvm::ScheduleDAGInstrs
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| H A D | BasicTTIImpl.h | 470 else if (ST->getSchedModel().LoopMicroOpBufferSize > 0)
471 MaxOps = ST->getSchedModel().LoopMicroOpBufferSize;
522 return getST()->getSchedModel().DefaultLoadLatency;
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| H A D | MachinePipeliner.h | 444 : STI(ST), SM(ST->getSchedModel()), UseDFA(ST->useDFAforSMS()),
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 197 const MCSchedModel SCModel = STI->getSchedModel();
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 417 const MCSchedModel &SM = STI.getSchedModel();
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 401 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
412 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ConditionalCompares.cpp | 936 SchedModel = MF.getSubtarget().getSchedModel();
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