1343171Sdim//===---------------------------- Context.cpp -------------------*- C++ -*-===// 2343171Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6343171Sdim// 7343171Sdim//===----------------------------------------------------------------------===// 8343171Sdim/// \file 9343171Sdim/// 10343171Sdim/// This file defines a class for holding ownership of various simulated 11343171Sdim/// hardware units. A Context also provides a utility routine for constructing 12343171Sdim/// a default out-of-order pipeline with fetch, dispatch, execute, and retire 13343171Sdim/// stages. 14343171Sdim/// 15343171Sdim//===----------------------------------------------------------------------===// 16343171Sdim 17343171Sdim#include "llvm/MCA/Context.h" 18343171Sdim#include "llvm/MCA/HardwareUnits/RegisterFile.h" 19343171Sdim#include "llvm/MCA/HardwareUnits/RetireControlUnit.h" 20343171Sdim#include "llvm/MCA/HardwareUnits/Scheduler.h" 21343171Sdim#include "llvm/MCA/Stages/DispatchStage.h" 22343171Sdim#include "llvm/MCA/Stages/EntryStage.h" 23343171Sdim#include "llvm/MCA/Stages/ExecuteStage.h" 24353358Sdim#include "llvm/MCA/Stages/MicroOpQueueStage.h" 25343171Sdim#include "llvm/MCA/Stages/RetireStage.h" 26343171Sdim 27343171Sdimnamespace llvm { 28343171Sdimnamespace mca { 29343171Sdim 30343171Sdimstd::unique_ptr<Pipeline> 31360784SdimContext::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) { 32343171Sdim const MCSchedModel &SM = STI.getSchedModel(); 33343171Sdim 34343171Sdim // Create the hardware units defining the backend. 35360784Sdim auto RCU = std::make_unique<RetireControlUnit>(SM); 36360784Sdim auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); 37360784Sdim auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, 38343171Sdim Opts.StoreQueueSize, Opts.AssumeNoAlias); 39360784Sdim auto HWS = std::make_unique<Scheduler>(SM, *LSU); 40343171Sdim 41343171Sdim // Create the pipeline stages. 42360784Sdim auto Fetch = std::make_unique<EntryStage>(SrcMgr); 43360784Sdim auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, 44343171Sdim *RCU, *PRF); 45353358Sdim auto Execute = 46360784Sdim std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis); 47360784Sdim auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); 48343171Sdim 49343171Sdim // Pass the ownership of all the hardware units to this Context. 50343171Sdim addHardwareUnit(std::move(RCU)); 51343171Sdim addHardwareUnit(std::move(PRF)); 52343171Sdim addHardwareUnit(std::move(LSU)); 53343171Sdim addHardwareUnit(std::move(HWS)); 54343171Sdim 55343171Sdim // Build the pipeline. 56360784Sdim auto StagePipeline = std::make_unique<Pipeline>(); 57343171Sdim StagePipeline->appendStage(std::move(Fetch)); 58353358Sdim if (Opts.MicroOpQueueSize) 59360784Sdim StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>( 60353358Sdim Opts.MicroOpQueueSize, Opts.DecodersThroughput)); 61343171Sdim StagePipeline->appendStage(std::move(Dispatch)); 62343171Sdim StagePipeline->appendStage(std::move(Execute)); 63343171Sdim StagePipeline->appendStage(std::move(Retire)); 64343171Sdim return StagePipeline; 65343171Sdim} 66343171Sdim 67343171Sdim} // namespace mca 68343171Sdim} // namespace llvm 69