/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMachineScheduler.cpp | 31 if (isADDIInstr(*FirstCand.SU->getInstr()) && 32 SecondCand.SU->getInstr()->mayLoad()) { 36 if (FirstCand.SU->getInstr()->mayLoad() && 37 isADDIInstr(*SecondCand.SU->getInstr())) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DebugHandlerBase.cpp | 231 Entries.front().getInstr()->getDebugVariable(); 234 if (!IsDescribedByReg(Entries.front().getInstr())) 235 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); 236 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { 241 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); 246 Pred.getInstr()->getDebugExpression()); 253 if (IsDescribedByReg(I->getInstr())) 255 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); 262 requestLabelBeforeInsn(Entry.getInstr()); 264 requestLabelAfterInsn(Entry.getInstr()); [all...] |
H A D | DbgEntityHistoryCalculator.cpp | 62 Entries.back().getInstr()->isIdenticalTo(MI)) { 64 << "\t" << Entries.back().getInstr() << "\t" << MI 78 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) 147 if (isDescribedByReg(*Entry.getInstr()) == RegNo) { 174 const MachineInstr &DV = *Entry.getInstr(); 366 dbgs() << " Instr: " << *Entry.getInstr();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonHazardRecognizer.cpp | 40 MachineInstr *MI = SU->getInstr(); 103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) 109 MachineInstr *MI = SU->getInstr(); 160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && 161 Resources->canReserveResources(*S.getSUnit()->getInstr())) {
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H A D | HexagonSubtarget.cpp | 146 MachineInstr &MI1 = *SU.getInstr(); 155 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); 183 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) 187 unsigned Type = HII.getType(*Inst2.getInstr()); 207 if (DAG->SUnits[su].getInstr()->isCall()) 210 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) 231 const MachineInstr *MI = DAG->SUnits[su].getInstr(); 273 MachineInstr &L0 = *S0.getInstr(); 286 MachineInstr &L1 = *S1.getInstr(); 321 MachineInstr *SrcInst = Src->getInstr(); [all...] |
H A D | HexagonMachineScheduler.cpp | 74 if (QII.mayBeCurLoad(*SUd->getInstr())) 77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) 98 if (!SU || !SU->getInstr()) 103 switch (SU->getInstr()->getOpcode()) { 105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) 119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); 157 switch (SU->getInstr()->getOpcode()) { 159 ResourcesModel->reserveResources(*SU->getInstr()); 181 LLVM_DEBUG(Packet[i]->getInstr() [all...] |
H A D | HexagonVLIWPacketizer.cpp | 416 if (PacketSU->getInstr()->isInlineAsm()) 510 assert(SUI->getInstr() && SUJ->getInstr()); 511 MachineInstr &MI = *SUI->getInstr(); 512 MachineInstr &MJ = *SUJ->getInstr(); 667 if (PacketSU->getInstr()->mayStore()) 753 MachineInstr &TempMI = *TempSU->getInstr(); 766 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) 820 MachineInstr &PacketMI = *PacketSU->getInstr(); 853 const MachineInstr &PI = *PacketSU->getInstr(); [all...] |
H A D | HexagonISelLoweringHVX.cpp | 483 SDValue HalfV0 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); 484 SDValue HalfV1 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); 533 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, 703 return getInstr(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG); 872 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, 996 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, 998 ByteVec = getInstr(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG); 1293 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); 1308 return getInstr(Hexagon::V6_vmpyih, dl, ResTy, {Vs, Vt}, DAG); 1315 SDValue T0 = getInstr(Hexago [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 37 MachineInstr *MI = SU->getInstr(); 82 MachineInstr *MI = SU->getInstr();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZHazardRecognizer.cpp | 105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) 169 OS << TII->getName(SU->getInstr()->getOpcode()); 204 if (has4RegOps(SU->getInstr())) 285 LastEmittedMI = SU->getInstr(); 291 LastEmittedMI = SU->getInstr(); 329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); 364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))
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H A D | SystemZHazardRecognizer.h | 123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600MachineScheduler.cpp | 161 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), 162 E = SU->getInstr()->operands_end(); It != E; ++It) { 195 if (isPhysicalRegCopy(SU->getInstr())) { 220 MachineInstr *MI = SU->getInstr(); 294 int Opcode = SU->getInstr()->getOpcode(); 323 InstructionsGroupCandidate.push_back(SU->getInstr()); 325 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { 394 AssignSlot(UnslotedSU->getInstr(), Slot); 443 InstructionsGroupCandidate.push_back(SU->getInstr());
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H A D | GCNDPPCombine.cpp | 209 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { 231 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { 241 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || 242 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { 257 DPPInst.getInstr()->eraseFromParent(); 260 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); 261 return DPPInst.getInstr(); 442 DPPMIs.push_back(UndefInst.getInstr());
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H A D | SIMachineScheduler.cpp | 271 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); 338 RPTracker.setPos(SU->getInstr()); 419 TopRPTracker.setPos(SU->getInstr()); 1145 if (SIInstrInfo::isEXP(*SU.getInstr())) { 1169 if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr())) 1354 MachineInstr *MI = SU->getInstr(); 1383 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); 1834 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { 1844 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { [all...] |
H A D | AMDGPUSubtarget.cpp | 725 MachineInstr *SrcI = Src->getInstr(); 726 MachineInstr *DstI = Dst->getInstr(); 769 MachineInstr &MI2 = *SU.getInstr(); 779 MachineInstr &MI1 = *SUa->getInstr(); 812 const MachineInstr *MI = SU->getInstr(); 817 const MachineInstr *MI = SU->getInstr(); 900 MachineInstr &MAI = *SU.getInstr();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | SlotIndexes.cpp | 124 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); 137 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); 216 MachineInstr *SlotMI = ListI->getInstr(); 254 if (itr->getInstr()) { 255 dbgs() << *itr->getInstr();
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H A D | MacroFusion.cpp | 94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " 95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); 161 if (DAG->ExitSU.getInstr()) 169 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); 188 const MachineInstr *DepMI = DepSU.getInstr();
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H A D | ScheduleDAGInstrs.cpp | 230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); 262 RegUse = UseSU->getInstr(); 265 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); 270 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, 277 if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle())) 290 MachineInstr *MI = SU->getInstr(); 313 !DefSU->getInstr()->registerDefIsDead(*Alias))) { 319 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); 394 MachineInstr *MI = SU->getInstr(); [all...] |
H A D | MachinePipeliner.cpp | 536 OrderedInsts.push_back(SU->getInstr()); 537 Cycles[SU->getInstr()] = Cycle; 538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); 665 MachineInstr &MI = *SU.getInstr(); 690 MachineInstr &LdMI = *Load->getInstr(); 765 MachineInstr *MI = I.getInstr(); 821 MachineInstr *PMI = PI.getSUnit()->getInstr(); 823 if (I.getInstr()->isPHI()) { 846 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, 851 Register OrigBase = I.getInstr() [all...] |
H A D | MachineScheduler.cpp | 782 MachineInstr *MI = SU->getInstr(); 932 const MachineInstr &MI = *SU.getInstr(); 1123 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); 1152 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); 1157 << *SU->getInstr(); 1168 if (EntrySU.getInstr() != nullptr) 1177 if (SchedModel.mustBeginGroup(SU.getInstr()) && 1178 SchedModel.mustEndGroup(SU.getInstr())) 1184 if (ExitSU.getInstr() != nullptr) 1349 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | DbgEntityHistoryCalculator.h | 60 const MachineInstr *getInstr() const { return Instr.getPointer(); } function in class:llvm::DbgValueHistoryMap::Entry
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H A D | SlotIndexes.h | 53 MachineInstr* getInstr() const { return mi; } function in class:llvm::IndexListEntry 402 return index.isValid() ? index.listEntry()->getInstr() : nullptr; 411 if (I->getInstr()) 592 assert(miEntry->getInstr() == &MI &&
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/ |
H A D | GIMatchDagPredicate.h | 90 const CodeGenInstruction *getInstr() const { return &Instr; } function in class:llvm::GIMatchDagOpcodePredicate
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFixIrreducibleControlFlow.cpp | 372 unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; 467 MIB.addMBB(MIB.getInstr() 468 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 437 .getInstr(); 441 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); 449 .getInstr();
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