Searched refs:getID (Results 1 - 25 of 134) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Option/
H A DOptSpecifier.h29 unsigned getID() const { return ID; } function in class:llvm::opt::OptSpecifier
31 bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
H A DOptTable.h77 unsigned id = Opt.getID();
H A DOption.h87 unsigned getID() const { function in class:llvm::opt::Option
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp62 return ContainedRegClasses.test(RC.getID());
75 assert((OtherRB.getID() != getID() || &OtherRB == this) &&
91 OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
/freebsd-11-stable/contrib/llvm-project/clang/lib/Frontend/
H A DTextDiagnosticPrinter.cpp58 if (Info.getID() == diag::fatal_too_many_errors) {
73 DiagnosticIDs::isBuiltinWarningOrExtension(Info.getID()) &&
74 !DiagnosticIDs::isDefaultMappingAsError(Info.getID())) {
79 StringRef Opt = DiagnosticIDs::getWarningOptionForDiag(Info.getID());
93 DiagnosticIDs::getCategoryNumberForDiag(Info.getID());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp60 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF);
95 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
330 && TLI->getRegClassFor(VT)->getID() == RCId)
341 && TLI->getRegClassFor(VT)->getID() == RCId)
361 RegBalance += rawRegPressureDelta(SU, RC->getID());
365 if ((RegPressure[RC->getID()] +
366 rawRegPressureDelta(SU, RC->getID()) > 0) &&
367 (RegPressure[RC->getID()] +
368 rawRegPressureDelta(SU, RC->getID()) >
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegisterBank.h47 unsigned getID() const { return ID; } function in class:llvm::RegisterBank
H A DRegisterBankInfo.h230 unsigned getID() const { return ID; }
254 return getID() != InvalidMappingID && OperandsMapping;
708 /// \p OpdMapper.getInstrMapping().getID() carries the information of
716 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp80 switch (RC->getID()) {
250 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
252 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
253 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
321 switch (RC.getID()) {
H A DHexagonMachineScheduler.cpp588 << ((Q.getID() == TopQID) ? "(top|" : "(bot|"));
597 if (Q.getID() == TopQID) {
640 if (Q.getID() == TopQID) {
676 if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 &&
692 if (Q.getID() == TopQID &&
696 } else if (Q.getID() == BotQID &&
705 if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) {
714 } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) {
731 if (Q.getID() == TopQID) {
798 if ((Q.getID()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Option/
H A DOption.cpp100 if (getID() == Opt.getID())
241 if (getID() == UnaliasedOption.getID())
H A DArgList.cpp40 OptRanges.insert(std::make_pair(O.getID(), emptyRange())).first->second;
54 OptRanges.erase(Id.getID());
61 auto I = OptRanges.find(Id.getID());
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/AST/
H A DCommentCommandTraits.h33 unsigned getID() const { function in struct:clang::comments::CommandInfo
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp195 assert((RegBank->getID() == ARM::GPRRegBankID ||
196 RegBank->getID() == ARM::FPRRegBankID) &&
199 if (RegBank->getID() == ARM::FPRRegBankID) {
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
282 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
287 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() !
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp538 unsigned PredID = Pred->getID();
542 if (PredID == P->getID())
550 return PredID == S.first->getID();
557 unsigned SuccID = Succ->getID();
561 if (SuccID == S.first->getID()) {
573 [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) &&
647 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID;
1305 if (!--TopDownBlock2Index[Pred->getID()])
1306 WorkList.push_back(Pred->getID());
1315 assert(TopDownBlock2Index[i] > TopDownBlock2Index[Pred->getID()]
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/freebsd-11-stable/contrib/llvm-project/lld/lib/Driver/
H A DDarwinLdDriver.cpp344 switch (kind->getOption().getID()) {
401 switch (minOS->getOption().getID()) {
706 if (mod->getOption().getID() == OPT_multi_module)
736 (pie->getOption().getID() == OPT_pie)) {
743 (pie->getOption().getID() == OPT_pie)) {
749 if (pie->getOption().getID() == OPT_no_pie) {
757 ctx.setPIE(pie->getOption().getID() == OPT_pie);
779 flagOn = arg->getOption().getID() == OPT_version_load_command;
780 flagOff = arg->getOption().getID() == OPT_no_version_load_command;
827 flagOn = arg->getOption().getID()
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/freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DStackMapPrinter.h39 W.startLine() << " Record ID: " << R.getID()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h74 const RCInfo &RCI = RegClass[RC->getID()];
H A DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } function in class:llvm::StackMapOpers
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } function in class:llvm::PatchPointOpers
177 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } function in class:llvm::StatepointOpers
H A DTargetRegisterInfo.h67 unsigned getID() const { return MC->getID(); } function in class:llvm::TargetRegisterClass
124 unsigned ID = RC->getID();
654 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
1117 bool isValid() const { return getID() != NumRegClasses; }
1120 unsigned getID() const { return ID; }
/freebsd-11-stable/contrib/llvm-project/clang/lib/ARCMigrate/
H A DTransProtectedScope.cpp119 if (I->getID() == diag::err_switch_into_protected_scope &&
132 assert(DiagI->getID() == diag::err_switch_into_protected_scope);
158 Pass.TA.clearDiagnostic(Diag.getID(), Diag.getLocation());
H A DPlistReporter.cpp96 DiagIDs.getCategoryNumberForDiag(D.getID()))) << '\n';
/freebsd-11-stable/contrib/llvm-project/lld/ELF/
H A DDriverUtils.cpp61 if (arg->getOption().getID() == OPT_color_diagnostics) {
63 } else if (arg->getOption().getID() == OPT_no_color_diagnostics) {
175 switch (arg->getOption().getID()) {
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DMemorySSA.h127 // getID()
217 inline unsigned getID() const;
338 OptimizedID = DMA->getID();
343 return getDefiningAccess() && OptimizedID == getDefiningAccess()->getID();
397 OptimizedID = MA->getID();
405 return getOptimized() && OptimizedID == getOptimized()->getID();
415 unsigned getID() const { return ID; } function in class:llvm::final
636 unsigned getID() const { return ID; } function in class:llvm::final
665 inline unsigned MemoryAccess::getID() const { function in class:llvm::MemoryAccess
669 return MD->getID();
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Analysis/
H A DProgramPoint.cpp72 Out << RS->getID(Context) << ", \"stmt\": ";
190 << "\", \"stmt_id\": " << S->getID(Context)

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