Searched refs:addReg (Results 1 - 25 of 234) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
63 .addReg(MI->getOperand(0).getReg())
64 .addReg(MI->getOperand(1).getReg())
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
110 .addReg(SystemZM
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
147 .addReg(Scratch)
148 .addReg(Mask);
150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB);
158 .addReg(Scratch, RegState::Kill)
159 .addReg(Mask2);
161 .addReg(Scratch, RegState::Kill)
162 .addReg(ShiftNewVal);
164 .addReg(Scratc
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H A DMipsFastISel.cpp221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
226 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
382 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
397 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
405 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg
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H A DMipsMachineFunction.cpp90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
91 .addReg(Mips::T9_64);
92 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
120 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
147 .addReg(Mips::V0).addReg(Mips::T9);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp96 .addReg(VE::SX11) // %sp
97 .addReg(VE::SX8) // %sl
106 .addReg(VE::SX14)
109 .addReg(VE::SX0)
114 .addReg(VE::SX61)
116 .addReg(VE::SX63);
118 .addReg(VE::SX61)
120 .addReg(VE::SX8);
122 .addReg(VE::SX61)
124 .addReg(V
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H A DVEFrameLowering.cpp52 .addReg(VE::SX11)
54 .addReg(VE::SX9);
56 .addReg(VE::SX11)
58 .addReg(VE::SX10);
60 .addReg(VE::SX11)
62 .addReg(VE::SX15);
64 .addReg(VE::SX11)
66 .addReg(VE::SX16);
68 .addReg(VE::SX11)
90 .addReg(V
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168 .addReg(Reg
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp251 .addReg(AddrReg);
257 .addReg(DestReg)
258 .addReg(IncrReg);
260 .addReg(ScratchReg)
265 .addReg(AddrReg)
266 .addReg(ScratchReg);
268 .addReg(ScratchReg)
269 .addReg(RISCV::X0)
285 .addReg(OldValReg)
286 .addReg(NewValRe
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc));
40 .addReg(SrcReg, getKillRegState(KillSrc));
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg)
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg)
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
95 .addReg(ScratchReg, RegState::Kill).addReg(DstRe
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp175 .addReg(TIP.first)
178 .addReg(0));
1007 .addReg(0));
1285 .addReg(MI->getOperand(0).getReg())
1289 .addReg(MI->getOperand(3).getReg()));
1301 .addReg(MI->getOperand(0).getReg())
1305 .addReg(MI->getOperand(3).getReg()));
1312 .addReg(ARM::LR)
1313 .addReg(ARM::PC)
1316 .addReg(
[all...]
H A DARMFrameLowering.cpp304 .addReg(Reg, RegState::Kill)
309 .addReg(Reg, RegState::Kill)
319 .addReg(Reg, RegState::Kill)
324 .addReg(Reg, RegState::Kill)
334 .addReg(Reg, RegState::Kill)
540 .addReg(ARM::R4, RegState::Implicit)
550 .addReg(ARM::R12, RegState::Kill)
551 .addReg(ARM::R4, RegState::Implicit)
557 .addReg(ARM::SP, RegState::Kill)
558 .addReg(AR
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp155 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
156 .addReg(DstLoReg, getKillRegState(DstIsKill))
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
160 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
161 .addReg(DstHiReg, getKillRegState(DstIsKill))
162 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
188 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
189 .addReg(DstLoReg, getKillRegState(DstIsKill))
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
196 .addReg(DstHiRe
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H A DAVRRelaxMemOperations.cpp100 .addReg(Ptr.getReg());
104 .addReg(Ptr.getReg(), RegState::Define)
105 .addReg(Ptr.getReg())
111 .addReg(Ptr.getReg())
112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill()));
H A DAVRFrameLowering.cpp72 .addReg(AVR::R29R28, RegState::Kill)
81 .addReg(AVR::R1R0, RegState::Kill)
88 .addReg(AVR::R0, RegState::Kill)
91 .addReg(AVR::R0, RegState::Define)
92 .addReg(AVR::R0, RegState::Kill)
93 .addReg(AVR::R0, RegState::Kill)
115 .addReg(AVR::SP)
132 .addReg(AVR::R29R28, RegState::Kill)
140 .addReg(AVR::R29R28)
173 .addReg(AV
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp372 .addReg(AArch64::X16)
373 .addReg(Reg)
378 .addReg(AArch64::W16)
379 .addReg(AArch64::X9)
380 .addReg(AArch64::X16)
386 .addReg(AArch64::XZR)
387 .addReg(AArch64::X16)
388 .addReg(Reg)
401 MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
406 .addReg(AArch6
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H A DAArch64SIMDInstrOpt.cpp447 .addReg(SrcReg2, Src2IsKill)
451 .addReg(SrcReg0, Src0IsKill)
452 .addReg(SrcReg1, Src1IsKill)
453 .addReg(DupDest, Src2IsKill);
459 .addReg(SrcReg1, Src1IsKill)
463 .addReg(SrcReg0, Src0IsKill)
464 .addReg(DupDest, Src1IsKill);
563 .addReg(StReg[0])
564 .addReg(StReg[1]);
566 .addReg(StRe
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp387 .addReg(SrcReg)
391 .addReg(SrcReg, RegState::Kill)
396 .addReg(SrcReg)
400 .addReg(SrcReg, RegState::Kill)
405 .addReg(SrcReg)
409 .addReg(SrcReg, RegState::Kill)
413 .addReg(DstReg, RegState::Kill)
979 MIB.addReg(MustSaveCRs[i], CrState);
981 .addReg(TempReg, getKillRegState(true))
983 .addReg(SPRe
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H A DPPCAsmPrinter.cpp400 .addReg(ScratchReg)
404 .addReg(ScratchReg)
405 .addReg(ScratchReg)
409 .addReg(ScratchReg)
410 .addReg(ScratchReg)
414 .addReg(ScratchReg)
415 .addReg(ScratchReg)
421 .addReg(PPC::X2)
423 .addReg(PPC::X1));
433 .addReg(PP
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp57 LiveRegs.addReg(CSRegs[i]);
107 .addReg(SpillReg, RegState::Kill)
108 .addReg(ScratchRsrcReg)
109 .addReg(SPReg)
127 .addReg(SpillReg, RegState::Kill)
128 .addReg(OffsetReg, RegState::Kill)
129 .addReg(ScratchRsrcReg)
130 .addReg(SPReg)
155 .addReg(ScratchRsrcReg)
156 .addReg(SPRe
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiFrameLowering.cpp79 .addReg(Src)
114 .addReg(Lanai::FP)
115 .addReg(Lanai::SP)
123 .addReg(Lanai::SP)
131 .addReg(Lanai::SP)
187 .addReg(Lanai::FP)
192 .addReg(Lanai::FP)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp71 .addReg(FrameReg)
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
78 .addReg(FrameReg)
84 .addReg(FrameReg)
107 .addReg(FrameReg)
108 .addReg(ScratchOffset, RegState::Kill)
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
114 .addReg(FrameReg)
115 .addReg(ScratchOffset, RegState::Kill)
120 .addReg(FrameRe
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp66 .addReg(SI.getOperand(1).getReg())
70 .addReg(SI.getOperand(0).getReg())
71 .addReg(AddrReg)
H A DARCRegisterInfo.cpp51 .addReg(BaseReg)
76 .addReg(BaseReg, RegState::Define)
77 .addReg(FrameReg)
94 .addReg(BaseReg, KillState)
107 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
108 .addReg(BaseReg, KillState)
116 .addReg(Reg, RegState::Define)
117 .addReg(FrameReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp134 .addReg(SrcReg);
189 .addReg(SPReg);
198 .addReg(SPReg)
199 .addReg(OffsetReg);
210 .addReg(WebAssembly::SP32)
211 .addReg(BitmaskReg);
218 .addReg(WebAssembly::SP32);
254 .addReg(hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32)
255 .addReg(OffsetReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
138 .addReg(FramePtr);
153 .addReg(SP::G1).addImm(LOX10(Offset));
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
156 .addReg(FramePtr);
190 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
202 .addReg(FrameReg).addImm(0);

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