/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
H A D | xray_trampoline_AArch64.S | 21 STP X1, X2, [SP, #-16]! 29 /* Load the address of _ZN6__xray19XRayPatchedFunctionE into X1 */ 30 LDR X1, =_ZN6__xray19XRayPatchedFunctionE 32 LDR X2, [X1] 37 X1=0 means that we are tracing an entry event */ 38 MOV X1, #0 39 /* Call the handler with 2 parameters in W0 and X1 */ 50 LDP X1, X2, [SP], #16 68 STP X1, X2, [SP, #-16]! 73 /* Load the address of _ZN6__xray19XRayPatchedFunctionE into X1 */ [all...] |
/freebsd-11-stable/crypto/openssl/crypto/seed/ |
H A D | seed_locl.h | 56 # define KEYSCHEDULE_UPDATE0(T0, T1, X1, X2, X3, X4, KC) \ 60 (T0) = ((X1) + (X3) - (KC)) & 0xffffffff; \ 63 # define KEYSCHEDULE_UPDATE1(T0, T1, X1, X2, X3, X4, KC) \ 64 (T0) = (X1); \ 65 (X1) = (((X1)>>8) ^ ((X2)<<24)) & 0xffffffff; \ 67 (T0) = ((X1) + (X3) - (KC)) & 0xffffffff; \ 98 # define E_SEED(T0, T1, X1, X2, X3, X4, rbase) \ 108 (X1) ^= (T0); \
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/freebsd-11-stable/contrib/libstdc++/include/ext/ |
H A D | typelist.h | 314 #define _GLIBCXX_TYPELIST_CHAIN2(X0, X1) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN1(X1) > 315 #define _GLIBCXX_TYPELIST_CHAIN3(X0, X1, X2) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN2(X1, X2) > 316 #define _GLIBCXX_TYPELIST_CHAIN4(X0, X1, X2, X3) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN3(X1, X2, X3) > 317 #define _GLIBCXX_TYPELIST_CHAIN5(X0, X1, X2, X3, X4) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN4(X1, X2, X3, X4) > 318 #define _GLIBCXX_TYPELIST_CHAIN6(X0, X1, X2, X3, X4, X5) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN5(X1, X [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/ToolDrivers/llvm-dlltool/ |
H A D | DlltoolDriver.cpp | 42 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ 43 {X1, X2, X10, X11, OPT_##ID, llvm::opt::Option::KIND##Class, \
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.cpp | 29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive"); 39 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
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H A D | RISCVFrameLowering.cpp | 360 SavedRegs.set(RISCV::X1); 374 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMCTargetDesc.cpp | 49 InitRISCVMCRegisterInfo(X, RISCV::X1);
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H A D | RISCVAsmBackend.cpp | 107 // c.jal $imm -> jal X1, $imm. 109 Res.addOperand(MCOperand::createReg(RISCV::X1));
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/freebsd-11-stable/sys/crypto/skein/ |
H A D | skein_block.c | 83 u64b_t X0,X1,X2,X3; /* local copy of context vars, for speed */ local 87 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; 110 X1 = w[1] + ks[1] + ts[0]; 131 X1 += ks[((R)+2) % 5] + ts[((R)+1) % 3]; \ 142 X1 += ks[r+(R)+1] + ts[r+(R)+0]; \ 216 ctx->X[1] = X1 ^ w[1]; 268 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ local 272 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3; 302 X1 = w[1] + ks[1]; 327 X1 [all...] |
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
H A D | FuzzerUtil.h | 67 const char *X1, const char *X2);
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/freebsd-11-stable/crypto/openssl/engines/ccgost/ |
H A D | gost89.c | 24 {0X1, 0XF, 0XD, 0X0, 0X5, 0X7, 0XA, 0X4, 0X9, 0X2, 0X3, 0XE, 0X6, 0XB, 27 {0XD, 0XB, 0X4, 0X1, 0X3, 0XF, 0X5, 0X9, 0X0, 0XA, 0XE, 0X7, 0X6, 0X8, 30 {0X4, 0XB, 0XA, 0X0, 0X7, 0X2, 0X1, 0XD, 0X3, 0X6, 0X8, 0X5, 0X9, 0XC, 33 {0X6, 0XC, 0X7, 0X1, 0X5, 0XF, 0XD, 0X8, 0X4, 0XA, 0X9, 0XE, 0X0, 0X3, 36 {0X7, 0XD, 0XA, 0X1, 0X0, 0X8, 0X9, 0XF, 0XE, 0X4, 0X6, 0XC, 0XB, 0X2, 39 {0X5, 0X8, 0X1, 0XD, 0XA, 0X3, 0X4, 0X2, 0XE, 0XF, 0XC, 0X7, 0X6, 0X0, 42 {0XE, 0XB, 0X4, 0XC, 0X6, 0XD, 0XF, 0XA, 0X2, 0X3, 0X8, 0X1, 0X0, 0X7, 45 {0X4, 0XA, 0X9, 0X2, 0XD, 0X8, 0X0, 0XE, 0X6, 0XB, 0X1, 0XC, 0X7, 0XF,
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ADT/ |
H A D | ImmutableList.h | 239 static bool isEqual(ImmutableList<T> X1, ImmutableList<T> X2) { argument 240 return X1 == X2;
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/freebsd-11-stable/contrib/llvm-project/lld/ELF/ |
H A D | DriverUtils.cpp | 45 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ 46 {X1, X2, X10, X11, OPT_##ID, opt::Option::KIND##Class, \
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIShrinkInstructions.cpp | 525 TargetInstrInfo::RegSubRegPair X1, Y1; local 526 X1 = getSubRegForIndex(X, Xsub, I, TRI, MRI); 530 .addDef(X1.Reg, 0, X1.SubReg) 533 .addReg(X1.Reg, 0, X1.SubReg).getInstr();
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/freebsd-11-stable/contrib/groff/src/preproc/html/ |
H A D | pre-html.cpp | 802 int X1; member in struct:imageItem 823 X1 = x1; 1006 if (i->X1 != -1) { 1008 int x1 = max(min(i->X1, i->X2) * image_res / postscriptRes 1015 int x2 = max(i->X1, i->X2) * image_res / postscriptRes
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/freebsd-11-stable/lib/libc/sparc64/fpu/ |
H A D | fpu.c | 97 #define X1(x) x macro 104 X1(FSR_NX),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/ToolDrivers/llvm-lib/ |
H A D | LibDriver.cpp | 48 #define OPTION(X1, X2, ID, KIND, GROUP, ALIAS, X7, X8, X9, X10, X11, X12) \ 49 {X1, X2, X10, X11, OPT_##ID, opt::Option::KIND##Class, \
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CallingConvention.cpp | 23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
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H A D | AArch64AsmPrinter.cpp | 474 .addReg(AArch64::X1) 493 .addReg(AArch64::X1) 1134 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); 1157 Blr.addOperand(MCOperand::createReg(AArch64::X1));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 92 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCSubtarget.h | 388 return IsPPC64 ? PPC::X1 : PPC::R1;
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H A D | PPCRegisterInfo.cpp | 408 if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects() 412 // and no inline asm which clobbers X1. 543 .addReg(PPC::X1); 573 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 575 .addReg(PPC::X1) 578 .addReg(PPC::X1) 1170 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
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/freebsd-11-stable/sys/crypto/aesni/ |
H A D | aesni_ghash.c | 164 __m128i X1, __m128i X2, __m128i X3, __m128i X4, __m128i *res) 173 H1_X1_lo = _mm_clmulepi64_si128(H1, X1, 0x00); 182 H1_X1_hi = _mm_clmulepi64_si128(H1, X1, 0x11); 192 tmp4 = _mm_shuffle_epi32(X1, 78); 194 tmp4 = _mm_xor_si128(tmp4, X1); 163 reduce4(__m128i H1, __m128i H2, __m128i H3, __m128i H4, __m128i X1, __m128i X2, __m128i X3, __m128i X4, __m128i *res) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 32 case AArch64::X1: return AArch64::W1; 72 case AArch64::W1: return AArch64::X1;
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/freebsd-11-stable/usr.sbin/bsdinstall/scripts/ |
H A D | auto | 187 "ThinkPad X220"|"ThinkPad T420"|"ThinkPad T520"|"ThinkPad W520"|"ThinkPad X1")
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