Searched refs:X0 (Results 1 - 25 of 36) sorted by relevance

12

/freebsd-11-stable/contrib/libstdc++/include/ext/
H A Dtypelist.h313 #define _GLIBCXX_TYPELIST_CHAIN1(X0) __gnu_cxx::typelist::chain<X0, __gnu_cxx::typelist::null_type>
314 #define _GLIBCXX_TYPELIST_CHAIN2(X0, X1) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN1(X1) >
315 #define _GLIBCXX_TYPELIST_CHAIN3(X0, X1, X2) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN2(X1, X2) >
316 #define _GLIBCXX_TYPELIST_CHAIN4(X0, X1, X2, X3) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN3(X1, X2, X3) >
317 #define _GLIBCXX_TYPELIST_CHAIN5(X0, X1, X2, X3, X4) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN
[all...]
/freebsd-11-stable/contrib/binutils/opcodes/
H A Dia64-opc-x.c25 #define X0 IA64_TYPE_X, 0 macro
65 {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL},
66 {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL},
67 {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL},
70 X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL
79 X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL
81 X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL
163 #undef X0 macro
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
79 markSuperRegs(Reserved, RISCV::X0); // zero
99 return PhysReg == RISCV::X0;
H A DRISCVAsmPrinter.cpp106 OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
H A DRISCVISelDAGToDAG.cpp72 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
80 // Only the first instruction has X0 as its source.
118 RISCV::X0, XLenVT);
H A DRISCVExpandPseudoInsts.cpp269 .addReg(RISCV::X0)
354 .addReg(RISCV::X0)
513 .addReg(RISCV::X0)
578 .addReg(RISCV::X0)
609 .addReg(RISCV::X0)
H A DRISCVInstrInfo.cpp171 Register SrcReg = RISCV::X0;
198 // Only the first instruction has X0 as its source.
500 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
782 .addReg(RISCV::X0, RegState::Define)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CleanupLocalDynamicTLSPass.cpp105 TII->get(TargetOpcode::COPY), AArch64::X0)
124 // Insert a copy from X0 to TLSBaseAddrReg for later.
128 .addReg(AArch64::X0);
H A DAArch64CollectLOH.cpp261 static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs");
263 if (AArch64::X0 <= Reg && Reg <= AArch64::X28)
264 return Reg - AArch64::X0;
H A DAArch64AsmPrinter.cpp284 // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
291 // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
322 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
473 .addReg(AArch64::X0)
485 if (Reg != AArch64::X0)
487 .addReg(AArch64::X0)
1128 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
1135 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
[all...]
H A DAArch64CallingConvention.cpp23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
H A DAArch64ISelLowering.h34 // offset of a variable into X0, using the TLSDesc model.
507 return AArch64::X0;
/freebsd-11-stable/sys/crypto/skein/
H A Dskein_block.c83 u64b_t X0,X1,X2,X3; /* local copy of context vars, for speed */ local
87 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3;
109 X0 = w[0] + ks[0]; /* do the first full key injection */
130 X0 += ks[((R)+1) % 5]; /* inject the key schedule value */ \
141 X0 += ks[r+(R)+0]; /* inject the key schedule value */ \
215 ctx->X[0] = X0 ^ w[0];
268 u64b_t X0,X1,X2,X3,X4,X5,X6,X7; /* local copy of vars, for speed */ local
272 Xptr[0] = &X0; Xptr[1] = &X1; Xptr[2] = &X2; Xptr[3] = &X3;
301 X0 = w[0] + ks[0]; /* do the first full key injection */
326 X0
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp87 // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
90 Res.addOperand(MCOperand::createReg(RISCV::X0));
94 // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
97 Res.addOperand(MCOperand::createReg(RISCV::X0));
101 // c.j $imm -> jal X0, $imm.
103 Res.addOperand(MCOperand::createReg(RISCV::X0));
H A DRISCVMCCodeEmitter.cpp129 // Emit JALR X0, X6, 0
130 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
/freebsd-11-stable/crypto/openssl/engines/ccgost/
H A Dgost89.c24 {0X1, 0XF, 0XD, 0X0, 0X5, 0X7, 0XA, 0X4, 0X9, 0X2, 0X3, 0XE, 0X6, 0XB,
27 {0XD, 0XB, 0X4, 0X1, 0X3, 0XF, 0X5, 0X9, 0X0, 0XA, 0XE, 0X7, 0X6, 0X8,
30 {0X4, 0XB, 0XA, 0X0, 0X7, 0X2, 0X1, 0XD, 0X3, 0X6, 0X8, 0X5, 0X9, 0XC,
33 {0X6, 0XC, 0X7, 0X1, 0X5, 0XF, 0XD, 0X8, 0X4, 0XA, 0X9, 0XE, 0X0, 0X3,
36 {0X7, 0XD, 0XA, 0X1, 0X0, 0X8, 0X9, 0XF, 0XE, 0X4, 0X6, 0XC, 0XB, 0X2,
39 {0X5, 0X8, 0X1, 0XD, 0XA, 0X3, 0X4, 0X2, 0XE, 0XF, 0XC, 0X7, 0X6, 0X0,
42 {0XE, 0XB, 0X4, 0XC, 0X6, 0XD, 0XF, 0XA, 0X2, 0X3, 0X8, 0X1, 0X0, 0X7,
45 {0X4, 0XA, 0X9, 0X2, 0XD, 0X8, 0X0, 0XE, 0X6, 0XB, 0X1, 0XC, 0X7, 0XF,
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp114 PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0);
H A Dxray_mips64.cpp123 PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCAsmPrinter.cpp1216 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1));
1217 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR8).addReg(PPC::X0));
1223 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0));
1302 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1));
1303 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR8).addReg(PPC::X0));
1309 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
31 case AArch64::X0: return AArch64::W0;
71 case AArch64::W0: return AArch64::X0;
/freebsd-11-stable/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-avx2.pl156 my ($X0,$X1,$X2,$X3, $Y0,$Y1,$Y2,$Y3,
181 vmovdqa 32*0(%rsi), $X0
193 vpunpcklqdq $X1, $X0, $T0 # T0 = [B2 A2 B0 A0]
195 vpunpckhqdq $X1, $X0, $T2 # T2 = [B3 A3 B1 A1]
203 vperm2i128 \$0x20, $T1, $T0, $X0 # X0 = [D0 C0 B0 A0]
214 vpand (%rdx), $X0, $T0 # out[0] = in[0] & mask;
215 vpsrlq \$29, $X0, $X0
216 vpand $T7, $X0,
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp71 Register Reg = RISCV::X0 + RegNo;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp97 {codeview::RegisterId::ARM64_X0, AArch64::X0},
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1647 Register SrcReg = RISCV::X0;
1658 // Only the first instruction has X0 as its source.
1808 .addReg(RISCV::X0)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp982 Value *X0; local
984 if (!tryToDecompose(OtherICmp, X0, UnsetBitsMask))
991 if (X1 == X0) {
994 } else if (match(X0, m_Trunc(m_Specific(X1)))) {

Completed in 360 milliseconds

12