Searched refs:V1 (Results 1 - 25 of 115) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DBasicValueFactory.cpp206 const llvm::APSInt& V1, const llvm::APSInt& V2) {
212 return &getValue( V1 * V2 );
217 return &getValue( V1 / V2 );
222 return &getValue( V1 % V2 );
225 return &getValue( V1 + V2 );
228 return &getValue( V1 - V2 );
239 if (Amt >= V1.getBitWidth())
243 if (V1.isSigned() && V1.isNegative())
246 if (V1
205 evalAPSInt(BinaryOperator::Opcode Op, const llvm::APSInt& V1, const llvm::APSInt& V2) argument
325 getPersistentSValPair(const SVal& V1, const SVal& V2) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
H A DConstantFold.h36 Constant *V1, Constant *V2);
40 Constant *ConstantFoldShuffleVectorInstruction(Constant *V1, Constant *V2,
47 Constant *ConstantFoldBinaryInstruction(unsigned Opcode, Constant *V1,
H A DConstantFold.cpp734 Constant *V1, Constant *V2) {
737 if (Cond->isAllOnesValue()) return V1;
743 for (unsigned i = 0, e = V1->getType()->getVectorNumElements(); i != e;++i){
745 Constant *V1Element = ConstantExpr::getExtractElement(V1,
762 if (Result.size() == V1->getType()->getVectorNumElements())
767 if (isa<UndefValue>(V1)) return V1;
770 if (isa<UndefValue>(V1)) return V2;
771 if (isa<UndefValue>(V2)) return V1;
772 if (V1
733 ConstantFoldSelectInstruction(Constant *Cond, Constant *V1, Constant *V2) argument
863 ConstantFoldShuffleVectorInstruction(Constant *V1, Constant *V2, Constant *Mask) argument
1471 evaluateFCmpRelation(Constant *V1, Constant *V2) argument
1560 evaluateICmpRelation(Constant *V1, Constant *V2, bool isSigned) argument
1887 const APInt &V1 = cast<ConstantInt>(C1)->getValue(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/
H A Dxxhash.cpp80 uint64_t V1 = Seed + PRIME64_1 + PRIME64_2; local
86 V1 = round(V1, endian::read64le(P));
96 H64 = rotl64(V1, 1) + rotl64(V2, 7) + rotl64(V3, 12) + rotl64(V4, 18);
97 H64 = mergeRound(H64, V1);
H A DFileUtilities.cpp91 double V1 = 0.0, V2 = 0.0; local
109 V1 = strtod(F1P, const_cast<char**>(&F1NumEnd));
118 V1 = strtod(&StrTmp[0], const_cast<char**>(&F1NumEnd));
145 if (AbsTolerance < std::abs(V1-V2)) {
149 Diff = std::abs(V1/V2 - 1.0);
150 else if (V1)
151 Diff = std::abs(V2/V1 - 1.0);
157 << "Compared: " << V1 << " and " << V2 << '\n'
158 << "abs. diff = " << std::abs(V1-V2) << " rel.diff = " << Diff << '\n'
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/
H A DProvenanceAnalysisEvaluator.cpp71 for (Value *V1 : Values) {
72 StringRef NameV1 = getName(V1);
78 if (PA.related(V1, V2, DL))
/freebsd-11-stable/contrib/subversion/subversion/libsvn_fs_fs/
H A Drep-cache-db.sql38 Same as in V1 schema, except that it uses the `WITHOUT ROWID` optimization:
57 /* Works for both V1 and V2 schemas. */
63 /* Works for both V1 and V2 schemas. */
68 /* Works for both V1 and V2 schemas. */
74 /* Works for both V1 and V2 schemas. */
79 /* Works for both V1 and V2 schemas. */
88 Works for both V1 and V2 schemas. */
94 /* Works for both V1 and V2 schemas. */
/freebsd-11-stable/contrib/llvm-project/clang/lib/Headers/
H A Dshaintrin.h20 #define _mm_sha1rnds4_epu32(V1, V2, M) \
21 __builtin_ia32_sha1rnds4((__v4si)(__m128i)(V1), (__v4si)(__m128i)(V2), (M))
H A Davxintrin.h1188 /// __m256d _mm256_permute2f128_pd(__m256d V1, __m256d V2, const int M);
1193 /// \param V1
1201 /// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the
1203 /// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the
1210 /// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the
1212 /// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the
1219 #define _mm256_permute2f128_pd(V1, V2, M) \
1220 (__m256d)__builtin_ia32_vperm2f128_pd256((__v4df)(__m256d)(V1), \
1229 /// __m256 _mm256_permute2f128_ps(__m256 V1, __m256 V2, const int M);
1234 /// \param V1
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPSInt.h339 inline bool operator==(int64_t V1, const APSInt &V2) { return V2 == V1; } argument
340 inline bool operator!=(int64_t V1, const APSInt &V2) { return V2 != V1; } argument
341 inline bool operator<=(int64_t V1, const APSInt &V2) { return V2 >= V1; } argument
342 inline bool operator>=(int64_t V1, const APSInt &V2) { return V2 <= V1; } argument
343 inline bool operator<(int64_t V1, const APSInt &V2) { return V2 > V1; } argument
344 operator >(int64_t V1, const APSInt &V2) argument
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H A DEquivalenceClasses.h217 member_iterator unionSets(const ElemTy &V1, const ElemTy &V2) { argument
218 iterator V1I = insert(V1), V2I = insert(V2);
241 // isEquivalent - Return true if V1 is equivalent to V2. This can happen if
242 // V1 is equal to V2 or if they belong to one equivalence class.
243 bool isEquivalent(const ElemTy &V1, const ElemTy &V2) const { argument
245 if (V1 == V2)
247 auto It = findLeader(V1);
/freebsd-11-stable/contrib/netbsd-tests/sbin/resize_ffs/
H A Dt_check.sh41 atf_check -o ignore -e ignore newfs -V1 -s 6144 -F ${IMG}
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGValue.h47 llvm::PointerIntPair<llvm::Value *, 2, Flavor> V1; member in class:clang::CodeGen::RValue
52 bool isScalar() const { return V1.getInt() == Scalar; }
53 bool isComplex() const { return V1.getInt() == Complex; }
54 bool isAggregate() const { return V1.getInt() == Aggregate; }
61 return V1.getPointer();
67 return std::make_pair(V1.getPointer(), V2.getPointer());
74 return Address(V1.getPointer(), CharUnits::fromQuantity(align));
78 return V1.getPointer();
88 ER.V1.setPointer(V);
89 ER.V1
93 getComplex(llvm::Value *V1, llvm::Value *V2) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp71 unsigned V0, V1; local
78 V1 = RegInfo.createVirtualRegister(RC);
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
92 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
120 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
H A DMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); local
79 V1 = RegInfo.createVirtualRegister(RC);
85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
90 .addReg(V1)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstrTypes.h231 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
233 return Create(Instruction::OPC, V1, V2, Name);\
237 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
239 return Create(Instruction::OPC, V1, V2, Name, BB);\
243 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
245 return Create(Instruction::OPC, V1, V2, Name, I);\
250 Value *V1, Value *V2,
253 BinaryOperator *BO = Create(Opc, V1, V2, Name);
258 static BinaryOperator *CreateFAddFMF(Value *V1, Value *V2, argument
261 return CreateWithCopiedFlags(Instruction::FAdd, V1, V
249 CreateWithCopiedFlags(BinaryOps Opc, Value *V1, Value *V2, Instruction *CopyO, const Twine &Name = �) argument
263 CreateFSubFMF(Value *V1, Value *V2, Instruction *FMFSource, const Twine &Name = �) argument
268 CreateFMulFMF(Value *V1, Value *V2, Instruction *FMFSource, const Twine &Name = �) argument
273 CreateFDivFMF(Value *V1, Value *V2, Instruction *FMFSource, const Twine &Name = �) argument
278 CreateFRemFMF(Value *V1, Value *V2, Instruction *FMFSource, const Twine &Name = �) argument
289 CreateNSW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = �) argument
295 CreateNSW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
301 CreateNSW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
308 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = �) argument
314 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
320 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
327 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = �) argument
333 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
339 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DBitTracker.cpp440 const BitValue &V1 = A1[I];
442 if (!V1.num() || !V2.num())
444 unsigned S = bool(V1) + bool(V2) + Carry;
449 const BitValue &V1 = A1[I];
453 if (V1.is(Carry))
456 Res[I] = BitValue::ref(V1);
473 const BitValue &V1 = A1[I];
475 if (!V1.num() || !V2.num())
477 unsigned S = bool(V1) - bool(V2) - Borrow;
482 const BitValue &V1
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/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/scudo/standalone/
H A Dinternal_defs.h86 scudo::u64 V1 = (scudo::u64)(C1); \
88 if (UNLIKELY(!(V1 Op V2))) { \
90 "(" #C1 ") " #Op " (" #C2 ")", V1, V2); \
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DConstantFolding.h89 Constant *ConstantFoldSelectInstruction(Constant *Cond, Constant *V1,
124 Constant *ConstantFoldShuffleVectorInstruction(Constant *V1, Constant *V2,
H A DBasicAliasAnalysis.h193 bool isValueEqualInPotentialCycles(const Value *V1, const Value *V2);
198 AliasResult aliasGEP(const GEPOperator *V1, LocationSize V1Size,
214 AliasResult aliasCheck(const Value *V1, LocationSize V1Size,
/freebsd-11-stable/contrib/ncurses/include/
H A DMKkey_defs.sh65 key_event kv1 str V1 KEY_EVENT + ----- We were interrupted by an event
/freebsd-11-stable/contrib/libreadline/examples/rlfe/
H A Drlfe.c138 #define DPRINT1(FMT, V1) (fprintf(logfile, FMT, V1), fflush(logfile))
139 #define DPRINT2(FMT, V1, V2) (fprintf(logfile, FMT, V1, V2), fflush(logfile))
142 #define DPRINT1(FMT, V1) ((void) 0) /* Do nothing */
143 #define DPRINT2(FMT, V1, V2) ((void) 0) /* Do nothing */
/freebsd-11-stable/contrib/dtc/
H A Ddtc-lexer.l25 %s V1
64 #define BEGIN_DEFAULT() DPRINT("<V1>\n"); \
65 BEGIN(V1); \
172 <V1>([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? {
/freebsd-11-stable/usr.bin/truss/
H A Dmips-freebsd.c124 retval[1] = regs.r_regs[V1];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3767 static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
3774 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
5976 static SDValue concatSubVectors(SDValue V1, SDValue V2, SelectionDAG &DAG,
5978 assert(V1.getValueType() == V2.getValueType() && "subvector type mismatch");
5979 EVT SubVT = V1.getValueType();
5984 SDValue V = insertSubVector(DAG.getUNDEF(VT), V1, 0, DAG, dl, SubVectorWidth);
6072 SDValue V1, SDValue V2) {
6075 return DAG.getVectorShuffle(VT, dl, V1, V2, Mask);
6080 SDValue V1, SDValue V2) {
6083 return DAG.getVectorShuffle(VT, dl, V1, V
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