Searched refs:UseMI (Results 1 - 25 of 61) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp31 MachineInstr *UseMI; member in struct:__anon2113::FoldCandidate
45 UseMI(MI), OpToFold(nullptr), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo),
95 MachineInstr *UseMI,
135 const MachineInstr &UseMI,
138 if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
141 unsigned Opc = UseMI.getOpcode();
172 const MachineInstr &UseMI,
176 (TII->isMUBUF(UseMI) || TII->isFLATScratch(UseMI)) &&
177 OpNo == AMDGPU::getNamedOperandIdx(UseMI
134 isInlineConstantIfFolded(const SIInstrInfo *TII, const MachineInstr &UseMI, unsigned OpNo, const MachineOperand &OpToFold) argument
171 frameIndexMayFold(const SIInstrInfo *TII, const MachineInstr &UseMI, int OpNo, const MachineOperand &OpToFold) argument
503 tryToFoldACImm(const SIInstrInfo *TII, const MachineOperand &OpToFold, MachineInstr *UseMI, unsigned UseOpIdx, SmallVectorImpl<FoldCandidate> &FoldList) argument
563 foldOperand( MachineOperand &OpToFold, MachineInstr *UseMI, int UseOpIdx, SmallVectorImpl<FoldCandidate> &FoldList, SmallVectorImpl<MachineInstr *> &CopiesToReplace) const argument
695 << "\\n into " << *UseMI << '\\n'); local
1155 MachineInstr *UseMI = Use->getParent(); local
1208 MachineInstr *UseMI = NonInlineUse->getParent(); local
1220 MachineInstr *UseMI = U->getParent(); local
[all...]
H A DSIFixSGPRCopies.cpp214 const auto *UseMI = MO.getParent(); local
215 if (UseMI == &MI)
217 if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
218 UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END ||
219 !TII->isOperandLegal(*UseMI, UseMI->getOperandNo(&MO), &Src))
770 const MachineInstr *UseMI = Use.getParent();
771 AllAGPRUses &= (UseMI->isCopy() &&
772 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) ||
774 if (UseMI
[all...]
H A DSIInstrInfo.cpp2315 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, argument
2340 unsigned Opc = UseMI.getOpcode();
2342 bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
2344 if (RI.isAGPR(*MRI, UseMI.getOperand(0).getReg())) {
2349 UseMI.setDesc(get(NewOpc));
2350 UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
2351 UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
2361 if (hasAnyModifiersSet(UseMI))
2367 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGP
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp92 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
96 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
187 MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode();
191 MI.getParent() != UseMI.getParent())
194 const MCInstrDesc &UseMID = UseMI.getDesc();
196 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
197 getBaseWithLongOffset(UseMI) < 0)
201 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
202 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
205 for (auto &Mo : UseMI
314 MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode(); local
399 MachineInstr *UseMI = OwnerN.Addr->getCode(); local
411 updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI) argument
622 MachineInstr *UseMI = UseIA.Addr->getCode(); local
668 xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI, NodeAddr<UseNode *> UseN, unsigned UseMOnum) argument
749 MachineInstr *UseMI = OwnerN.Addr->getCode(); local
[all...]
H A DHexagonConstExtenders.cpp319 MachineInstr *UseMI = nullptr; member in struct:__anon2229::HexagonConstExtenders::ExtDesc
332 return UseMI->getOperand(OpNum);
335 return UseMI->getOperand(OpNum);
1103 unsigned IdxOpc = getRegOffOpcode(ED.UseMI->getOpcode());
1113 if (!ED.UseMI->mayLoad() && !ED.UseMI->mayStore())
1218 ED.UseMI = &MI;
1285 if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) {
1490 MachineBasicBlock *DomB = ED0.UseMI->getParent();
1491 RefMIs.insert(ED0.UseMI);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.h33 MachineBasicBlock::iterator &UseMI,
H A DMips16RegisterInfo.cpp59 MachineBasicBlock::iterator &UseMI,
65 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
56 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp187 MachineInstr *DefMI = nullptr, *UseMI = nullptr; local
199 if (UseMI && UseMI != MI)
204 UseMI = MI;
207 if (!DefMI || !UseMI)
213 LIS.getInstructionIndex(*UseMI)))
217 // Assume there are stores between DefMI and UseMI.
223 << " into single use: " << *UseMI); local
226 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
229 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Op
[all...]
H A DMachineTraceMetrics.cpp649 // Get the input data dependencies that must be ready before UseMI can issue.
650 // Return true if UseMI has any physreg operands.
651 static bool getDataDeps(const MachineInstr &UseMI,
655 if (UseMI.isDebugInstr())
659 for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),
660 E = UseMI.operands_end(); I != E; ++I) {
673 Deps.push_back(DataDep(MRI, Reg, UseMI.getOperandNo(I)));
681 static void getPHIDeps(const MachineInstr &UseMI,
688 assert(UseMI.isPHI() && UseMI
[all...]
H A DOptimizePHIs.cpp157 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
158 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle))
H A DTargetSchedule.cpp186 const MachineInstr *UseMI, unsigned UseOperIdx) const {
193 if (UseMI) {
195 *UseMI, UseOperIdx);
225 if (!UseMI)
229 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
232 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
184 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const argument
H A DDetectDeadLanes.cpp423 const MachineInstr &UseMI = *MO.getParent(); local
424 if (UseMI.isKill())
428 if (lowersToCopies(UseMI)) {
429 assert(UseMI.getDesc().getNumDefs() == 1);
430 const MachineOperand &Def = *UseMI.defs().begin();
437 if (lowersToCopies(UseMI)) {
439 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
441 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
H A DMachineLICM.cpp1005 for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) {
1006 if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI))
1102 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
1104 if (UseMI.isPHI()) {
1107 if (CurLoop->contains(&UseMI))
1112 if (isExitBlock(UseMI.getParent()))
1117 if (UseMI.isCopy() && CurLoop->contains(&UseMI))
1118 Work.push_back(&UseMI);
[all...]
H A DMachineSSAUpdater.cpp224 MachineInstr *UseMI = U.getParent(); local
226 if (UseMI->isPHI()) {
227 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U);
230 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
H A DRegisterScavenging.cpp310 MachineBasicBlock::iterator &UseMI) {
367 UseMI = RestorePointMI;
463 MachineBasicBlock::iterator &UseMI) {
508 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
525 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,
527 II = std::prev(UseMI);
559 MachineBasicBlock::iterator UseMI; local
560 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
571 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
572 Scavenged.Restore = &*std::prev(UseMI);
307 findSurvivorReg(MachineBasicBlock::iterator StartMI, BitVector &Candidates, unsigned InstrLimit, MachineBasicBlock::iterator &UseMI) argument
588 MachineBasicBlock::iterator UseMI; local
[all...]
H A DPeepholeOptimizer.cpp501 MachineInstr *UseMI = UseMO.getParent(); local
502 if (UseMI == &MI)
505 if (UseMI->isPHI()) {
531 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
534 MachineBasicBlock *UseMBB = UseMI->getParent();
537 if (!LocalMIs.count(UseMI))
574 MachineInstr *UseMI = UseMO->getParent(); local
575 MachineBasicBlock *UseMBB = UseMI->getParent();
586 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI
[all...]
H A DTailDuplicator.cpp219 MachineInstr *UseMI = UseMO.getParent(); local
221 if (UseMI->isDebugValue()) {
226 UseMI->eraseFromParent();
229 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
297 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
298 if (UseMI.isDebugValue())
300 if (UseMI.getParent() != BB)
H A DRegisterCoalescer.cpp846 MachineInstr *UseMI = MO.getParent(); local
847 unsigned OpNo = &MO - &UseMI->getOperand(0);
848 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
853 if (UseMI->isRegTiedToDefOperand(OpNo))
895 MachineInstr *UseMI = UseMO.getParent(); local
896 if (UseMI->isDebugValue()) {
902 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
913 if (UseMI == CopyMI)
915 if (!UseMI->isCopy())
917 if (UseMI
927 LLVM_DEBUG(dbgs() << "\\t\\tnoop: " << DefIdx << '\\t' << *UseMI); local
1510 MachineInstr *UseMI = UseMO.getParent(); local
1518 MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI); local
1702 MachineInstr *UseMI = &*(I++); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp151 MachineInstr &UseMI = *MOUse.getParent(); local
152 if (MRI->hasOneUse(Reg) && !UseMI.isPHI())
153 InsertMBB->insert(InsertMBB->SkipPHIsAndLabels(UseMI), LocalizedMI);
189 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
190 if (!UseMI.isPHI())
191 Users.insert(&UseMI);
H A DCombinerHelper.cpp354 MachineInstr &UseMI = *UseMO.getParent(); local
356 MachineBasicBlock *InsertBB = UseMI.getParent();
359 if (UseMI.isPHI()) {
431 for (auto &UseMI : MRI.use_instructions(LoadValue.getReg())) {
432 if (UseMI.getOpcode() == TargetOpcode::G_SEXT ||
433 UseMI.getOpcode() == TargetOpcode::G_ZEXT ||
434 UseMI.getOpcode() == TargetOpcode::G_ANYEXT) {
436 MRI.getType(UseMI.getOperand(0).getReg()),
437 UseMI.getOpcode(), &UseMI);
493 MachineInstr *UseMI = UseMO->getParent(); local
562 isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI) argument
575 dominates(MachineInstr &DefMI, MachineInstr &UseMI) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); local
123 if (UseMI->getParent() != MBB)
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
127 Reg = UseMI->getOperand(0).getReg();
130 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
131 if (UseMI->getParent() != MBB)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h212 /// StartMI. UseMI is set to the instruction where the search stopped.
218 MachineBasicBlock::iterator &UseMI);
227 /// \p UseMI.
230 MachineBasicBlock::iterator &UseMI);
H A DTargetSchedule.h172 /// when the operand indices are already known. UseMI may be NULL for an
175 const MachineInstr *UseMI, unsigned UseOperIdx)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h78 /// Returns true if \p DefMI precedes \p UseMI or they are the same
80 bool isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI);
82 /// Returns true if \p DefMI dominates \p UseMI. By definition an
88 bool dominates(MachineInstr &DefMI, MachineInstr &UseMI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp676 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
677 int UseIdx = SwapMap[&UseMI];
689 LLVM_DEBUG(UseMI.dump());
719 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
720 int UseIdx = SwapMap[&UseMI];
761 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
762 int UseIdx = SwapMap[&UseMI];
766 LLVM_DEBUG(UseMI.dump());

Completed in 395 milliseconds

123