Searched refs:TrueReg (Results 1 - 16 of 16) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h228 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
H A DSystemZInstrInfo.cpp535 unsigned TrueReg, unsigned FalseReg,
547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
570 unsigned TrueReg,
590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
592 TrueReg = TReg;
604 .addReg(FalseReg).addReg(TrueReg)
533 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Pred, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
566 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef<MachineOperand> Pred, unsigned TrueReg, unsigned FalseReg) const argument
H A DSystemZISelLowering.cpp6814 Register TrueReg = MI->getOperand(1).getReg(); local
6821 std::swap(TrueReg, FalseReg);
6823 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end())
6824 TrueReg = RegRewriteTable[TrueReg].first;
6831 .addReg(TrueReg).addMBB(TrueMBB)
6835 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
6920 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp757 unsigned TrueReg, unsigned FalseReg,
770 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
795 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
803 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
804 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
856 SecondReg = SwapOps ? TrueReg : FalseReg;
2224 unsigned TrueReg, unsigned FalseReg,
2231 return Imm1 < Imm2 ? TrueReg : FalseReg;
2233 return Imm1 > Imm2 ? TrueReg
755 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
792 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &dl, unsigned DestReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument
[all...]
H A DPPCMIPeephole.cpp459 unsigned TrueReg = local
461 if (!Register::isVirtualRegister(TrueReg))
463 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
522 unsigned TrueReg = local
524 if (!Register::isVirtualRegister(TrueReg))
526 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
H A DPPCInstrInfo.h279 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h197 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
H A DAArch64InstrInfo.cpp499 unsigned TrueReg, unsigned FalseReg,
505 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
519 if (canFoldIntoCSel(MRI, TrueReg))
543 unsigned TrueReg, unsigned FalseReg) const {
646 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
651 TrueReg = FalseReg;
665 MRI.constrainRegClass(TrueReg, RC);
670 .addReg(TrueReg)
497 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
539 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp789 auto TrueReg = MIB->getOperand(2).getReg(); local
791 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
796 .addUse(TrueReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h297 unsigned TrueReg, unsigned FalseReg,
304 unsigned TrueReg, unsigned FalseReg) const override;
309 unsigned TrueReg, unsigned FalseReg) const;
H A DSIInstrInfo.cpp823 unsigned TrueReg,
841 .addReg(TrueReg)
856 .addReg(TrueReg)
870 .addReg(TrueReg)
884 .addReg(TrueReg)
896 .addReg(TrueReg)
916 .addReg(TrueReg)
934 .addReg(TrueReg)
2128 unsigned TrueReg, unsigned FalseReg,
2135 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
819 insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument
2126 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
2166 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp895 unsigned TrueReg = getRegForValue(Select->getTrueValue()); local
896 if (TrueReg == 0)
904 std::swap(TrueReg, FalseReg);
938 .addReg(TrueReg)
H A DWebAssemblyISelLowering.cpp387 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; local
393 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
427 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute);
431 .addReg(TrueReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h312 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
H A DX86InstrInfo.cpp2832 unsigned TrueReg, unsigned FalseReg,
2846 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2869 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2879 .addReg(TrueReg)
2830 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
2866 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h830 /// instruction that chooses between TrueReg and FalseReg based on the
833 /// When successful, also return the latency in cycles from TrueReg,
841 /// @param TrueReg Virtual register to select when Cond is true.
844 /// @param TrueCycles Latency from TrueReg to select output.
847 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
853 /// Insert a select instruction into MBB before I that will copy TrueReg to
866 /// @param TrueReg Virtual register to copy when Cond is true.
871 unsigned TrueReg, unsigned FalseReg) const {
846 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
868 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument

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