Searched refs:Tmp0 (Results 1 - 10 of 10) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp3609 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
3610 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3612 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)};
3645 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
3646 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3647 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
3678 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
3679 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3680 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
4226 SDValue Tmp0, Tmp local
4668 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
4721 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
4803 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
4908 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
4916 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; local
5161 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
[all...]
H A DX86ISelLowering.cpp[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp815 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); local
816 Tmp0 = Builder.CreateMul(Tmp0, TIdX);
818 Value *TID = Builder.CreateAdd(Tmp0, Tmp1);
H A DAMDGPUCodeGenPrepare.cpp824 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
825 Value *Tmp0 = Builder.CreateSelect(RCP_HI_0_CC, RCP_A_E, RCP_S_E); local
827 // Quotient = mulhu(Tmp0, Num)
828 Value *Quotient = getMulHu(Builder, Tmp0, Num);
H A DAMDGPUISelLowering.cpp1895 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1896 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT), local
1899 // Quotient = mulhu(Tmp0, Num)
1900 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
2112 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); local
2122 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2225 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); local
2227 DAG.getConstant(0, SL, MVT::i64), Tmp0,
H A DAMDGPULegalizerInfo.cpp1463 auto Tmp0 = B.buildAnd(S64, Src, Not);
1469 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp254 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); local
256 Value *SR = Builder.CreateSub(Tmp0, Tmp1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp387 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; local
388 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
399 Tmp0 = InReg;
401 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg);
405 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1);
415 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5503 SDValue Tmp0 = Op.getOperand(0); local
5508 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5509 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5523 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5534 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5545 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5568 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5569 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp7589 SDValue Tmp0 = getValue(I.getArgOperand(0));
7591 EVT VT = Tmp0.getValueType();
7592 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));

Completed in 321 milliseconds