/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRMCAsmInfo.cpp | 19 AVRMCAsmInfo::AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { argument
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H A D | AVRMCAsmInfo.h | 25 explicit AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreSubtarget.cpp | 27 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU, argument 29 : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCSubtarget.cpp | 27 ARCSubtarget::ARCSubtarget(const Triple &TT, const std::string &CPU, argument 29 : ARCGenSubtargetInfo(TT, CPU, FS), FrameLowering(*this),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetMachine.cpp | 90 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { argument 91 if (TT.isOSBinFormatMachO()) { 92 if (TT.getArch() == Triple::x86_64) 97 if (TT.isOSFreeBSD()) 99 if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU()) 101 if (TT.isOSSolaris()) 103 if (TT.isOSFuchsia()) 105 if (TT 112 computeDataLayout(const Triple &TT) argument 160 getEffectiveRelocModel(const Triple &TT, bool JIT, Optional<Reloc::Model> RM) argument 216 X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) argument 420 const Triple &TT = TM->getTargetTriple(); local 475 const Triple &TT = TM->getTargetTriple(); local 531 const Triple &TT = TM->getTargetTriple(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVSubtarget.cpp | 33 const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) { 35 bool Is64Bit = TT.isArch64Bit(); 45 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); 46 RISCVFeatures::validate(TT, getFeatureBits()); 50 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS, argument 52 : RISCVGenSubtargetInfo(TT, CPU, FS), 54 FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)), 32 initializeSubtargetDependencies( const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySubtarget.cpp | 38 WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT, argument 42 : WebAssemblyGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), 43 TargetTriple(TT), FrameLowering(),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCAsmInfo.h | 25 explicit HexagonMCAsmInfo(const Triple &TT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCAsmInfo.cpp | 15 SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) { argument
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H A D | SystemZMCAsmInfo.h | 20 explicit SystemZMCAsmInfo(const Triple &TT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCAsmInfo.h | 25 explicit XCoreMCAsmInfo(const Triple &TT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/ |
H A D | ARCMCAsmInfo.h | 26 explicit ARCMCAsmInfo(const Triple &TT);
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H A D | ARCMCTargetDesc.cpp | 43 static MCRegisterInfo *createARCMCRegisterInfo(const Triple &TT) { argument 49 static MCSubtargetInfo *createARCMCSubtargetInfo(const Triple &TT, argument 51 return createARCMCSubtargetInfoImpl(TT, CPU, FS); 55 const Triple &TT, 57 MCAsmInfo *MAI = new ARCMCAsmInfo(TT); 54 createARCMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCAsmInfo.cpp | 18 MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT, argument
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H A D | MSP430MCAsmInfo.h | 25 explicit MSP430MCAsmInfo(const Triple &TT, const MCTargetOptions &Options);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFMCAsmInfo.h | 24 explicit BPFMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { argument 25 if (TT.getArch() == Triple::bpfeb)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMCTargetDesc.cpp | 47 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { argument 54 const Triple &TT, 56 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); 65 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, argument 69 CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; 70 return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS); 83 const Triple &TT = STI.getTargetTriple(); local 84 if (TT.isOSBinFormatELF()) 53 createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCAsmBackend.cpp | 80 Triple TT; member in class:__anon2780::PPCAsmBackend 82 PPCAsmBackend(const Target &T, const Triple &TT) argument 83 : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big), 84 TT(TT) {} 205 DarwinPPCAsmBackend(const Target &T, const Triple &TT) argument 206 : PPCAsmBackend(T, TT) {} 210 bool Is64 = TT.isPPC64(); 220 ELFPPCAsmBackend(const Target &T, const Triple &TT) : PPCAsmBackend(T, TT) {} argument 234 XCOFFPPCAsmBackend(const Target &T, const Triple &TT) argument 260 const Triple &TT = STI.getTargetTriple(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430TargetMachine.cpp | 35 static std::string computeDataLayout(const Triple &TT, StringRef CPU, argument 40 MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, argument 46 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, 50 Subtarget(TT, CPU, FS, *this) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/ |
H A D | JITTargetMachineBuilder.cpp | 17 JITTargetMachineBuilder::JITTargetMachineBuilder(Triple TT) argument 18 : TT(std::move(TT)) { 45 auto *TheTarget = TargetRegistry::lookupTarget(TT.getTriple(), ErrMsg); 50 TheTarget->createTargetMachine(TT.getTriple(), CPU, Features.getString(),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64TargetStreamer.cpp | 61 const Triple &TT = STI.getTargetTriple(); local 62 if (TT.isOSBinFormatELF()) 64 if (TT.isOSBinFormatCOFF())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCAsmInfo.cpp | 17 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT, argument 20 CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4; 28 MaxInstLength = (TT.getArch() == Triple::amdgcn) ? 20 : 16;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VESubtarget.cpp | 41 VESubtarget::VESubtarget(const Triple &TT, const std::string &CPU, argument 43 : VEGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 36 const Triple &TT, 38 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 46 const Triple &TT, 48 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 61 static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) { argument 68 createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument 70 CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8"; 71 return createSparcMCSubtargetInfoImpl(TT, CPU, FS); 35 createSparcMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument 45 createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/ |
H A D | MCRelocationInfo.cpp | 27 MCRelocationInfo *llvm::createMCRelocationInfo(const Triple &TT, argument
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