Searched refs:TSR (Results 1 - 1 of 1) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 204 unsigned TSR, unsigned FR, unsigned FSR);
779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {
805 .addReg(TR, 0, TSR)
818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; local
824 TR = RO.getReg(), TSR = RO.getSubReg();
833 TR = SR, TSR = SSR;
844 FP.PredR, TR, TSR, FR, FSR);
847 MuxSR = TSR;
777 buildMux(MachineBasicBlock *B, MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) argument
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