| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 928 VectorType *SubVT = VectorType::get(VT->getElementType(), NumSubElts); local
1009 Instruction::InsertElement, SubVT, i);
1025 Instruction::ExtractElement, SubVT, i);
1038 SubVT = VectorType::get(I8Type, NumSubElts);
1052 Instruction::ExtractElement, SubVT, i);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2614 EVT SubVT = ShiftAmt->getValueType(0); local
2615 if (SubVT == MVT::i32) {
2619 assert(SubVT == MVT::i64);
2624 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT);
2626 CurDAG->getMachineNode(NegOpc, DL, SubVT, Zero, Add1);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2148 EVT SubVT = N->getValueType(0); local
2158 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
2160 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
2162 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
3886 EVT SubVT = Mask->getValueType(0); local
3887 SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
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| H A D | TargetLowering.cpp | 924 EVT SubVT = Sub.getValueType(); local
925 unsigned NumSubElts = SubVT.getVectorNumElements();
978 EVT SubVT = Op.getOperand(0).getValueType(); local
980 unsigned NumSubElts = SubVT.getVectorNumElements();
2310 EVT SubVT = Op.getOperand(0).getValueType(); local
2312 unsigned NumSubElts = SubVT.getVectorNumElements();
2330 EVT SubVT = Sub.getValueType(); local
2331 unsigned NumSubElts = SubVT.getVectorNumElements();
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| H A D | SelectionDAG.cpp | 2688 EVT SubVT = N0.getValueType();
2689 unsigned SubBitWidth = SubVT.getScalarSizeInBits();
2692 if (!(SubVT.isInteger() || SubVT.isFloatingPoint()))
9195 EVT SubVT = EVT::getVectorVT(*getContext(), OpSVT, NumSubElts);
9196 if (!TLI->isExtractSubvectorCheap(SubVT, OpVT, 0))
9200 ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op,
|
| H A D | DAGCombiner.cpp | 18287 static SDValue getSubVectorSrc(SDValue V, SDValue Index, EVT SubVT) { argument
18289 V.getOperand(1).getValueType() == SubVT && V.getOperand(2) == Index) {
18294 V.getOperand(0).getValueType() == SubVT &&
18295 (IndexC->getZExtValue() % SubVT.getVectorNumElements()) == 0) {
18296 uint64_t SubIdx = IndexC->getZExtValue() / SubVT.getVectorNumElements();
18316 EVT SubVT = Extract->getValueType(0); local
18317 if (!TLI.isOperationLegalOrCustom(BinOpcode, SubVT))
18320 SDValue Sub0 = getSubVectorSrc(Bop0, Index, SubVT);
18321 SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT);
18332 return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub
19559 EVT SubVT = local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | LoopVectorize.cpp | 2304 VectorType *SubVT = VectorType::get(ScalarTy, VF);
2322 if (StoredVec->getType() != SubVT)
2323 StoredVec = createBitOrPointerCast(StoredVec, SubVT, DL);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3738 EVT SubVT = ShiftAmt.getValueType(); local
3739 SDValue Zero = CurDAG->getConstant(0, DL, SubVT);
3740 SDValue Neg = CurDAG->getNode(ISD::SUB, DL, SubVT, Zero, Add1);
|
| H A D | X86ISelLowering.cpp | 5745 EVT SubVT = Sub.getValueType();
5748 if (VT.getSizeInBits() == (SubVT.getSizeInBits() * 2) &&
5751 Src.getOperand(1).getValueType() == SubVT &&
5979 EVT SubVT = V1.getValueType();
5980 EVT SubSVT = SubVT.getScalarType();
5981 unsigned SubNumElts = SubVT.getVectorNumElements();
5982 unsigned SubVectorWidth = SubVT.getSizeInBits();
7246 EVT SubVT = Sub.getValueType();
7247 unsigned NumSubElts = SubVT.getVectorNumElements();
7640 EVT SubVT
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8053 EVT SubVT = SubV1.getValueType(); local
8061 ShuffleMask, SubVT, WhichResult, isV_UNDEF)) {
8066 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
8343 EVT SubVT = MVT::getVectorVT(ElType, NumElts); local
8344 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT);
8348 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt,
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