Searched refs:Stages (Results 1 - 10 of 10) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | Pipeline.cpp | 27 for (auto &S : Stages)
32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) {
38 assert(!Stages.empty() && "Unexpected empty pipeline found!");
54 for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) {
61 Stage &FirstStage = *Stages[0];
66 for (const std::unique_ptr<Stage> &S : Stages) {
77 if (!Stages.empty()) {
78 Stage *Last = Stages.back().get();
82 Stages
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 110 const InstrStage *Stages = nullptr; ///< Array of stages selected member in class:llvm::InstrItineraryData
119 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
134 return Stages + StageIdx;
140 return Stages + StageIdx;
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| H A D | MCSubtargetInfo.h | 86 const InstrStage *Stages; // Instruction itinerary stages member in class:llvm::MCSubtargetInfo
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Pipeline.h | 20 #include "llvm/MCA/Stages/Stage.h"
57 SmallVector<std::unique_ptr<Stage>, 8> Stages; member in class:llvm::mca::Pipeline
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 229 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; local
230 if ((int)CurStage > Schedule.getNumStages() - 1 && Stages.first == 0 &&
231 Stages.second)
233 return Stages.first;
243 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; local
244 if (Stages.second)
245 return Stages.first;
246 return Stages.first - 1;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 217 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
311 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
315 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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| /freebsd-11-stable/lib/clang/libllvm/ |
| H A D | Makefile | 764 SRCS_EXT+= MCA/Stages/DispatchStage.cpp
765 SRCS_EXT+= MCA/Stages/EntryStage.cpp
766 SRCS_EXT+= MCA/Stages/ExecuteStage.cpp
767 SRCS_EXT+= MCA/Stages/InstructionTables.cpp
768 SRCS_EXT+= MCA/Stages/MicroOpQueueStage.cpp
769 SRCS_EXT+= MCA/Stages/RetireStage.cpp
770 SRCS_EXT+= MCA/Stages/Stage.cpp
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 531 DenseMap<MachineInstr *, int> Cycles, Stages; local
538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU);
544 Stages[KV.first] = Stages[KV.second];
549 std::move(Stages));
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 9217 unsigned Stages = Log2_32(Op.getValueType().getVectorNumElements());
9219 for (unsigned i = 0; i < Stages; ++i) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | [all...] |
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