Searched refs:ScratchReg (Results 1 - 20 of 20) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp239 Register ScratchReg = MI.getOperand(1).getReg(); local
256 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
259 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
260 .addReg(ScratchReg)
264 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
266 .addReg(ScratchReg);
268 .addReg(ScratchReg)
276 Register MaskReg, Register ScratchReg) {
277 assert(OldValReg != ScratchReg && "OldValReg and ScratchReg mus
273 insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, MachineBasicBlock *MBB, Register DestReg, Register OldValReg, Register NewValReg, Register MaskReg, Register ScratchReg) argument
301 Register ScratchReg = MI.getOperand(1).getReg(); local
553 Register ScratchReg = MI.getOperand(1).getReg(); local
[all...]
H A DRISCVRegisterInfo.cpp135 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); local
136 TII->movImm(MBB, II, DL, ScratchReg, Offset);
137 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
139 .addReg(ScratchReg, RegState::Kill);
141 FrameReg = ScratchReg;
H A DRISCVFrameLowering.cpp93 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
94 TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
97 .addReg(ScratchReg, RegState::Kill)
H A DRISCVInstrInfo.cpp399 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); local
402 MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
405 .addReg(ScratchReg, RegState::Kill)
411 MRI.replaceRegWith(ScratchReg, Scav);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp50 Register ScratchReg = MI->getOperand(4).getReg(); local
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg)
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg)
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
H A DBPFISelLowering.cpp592 unsigned ScratchReg; local
609 ScratchReg = MRI.createVirtualRegister(&BPF::GPRRegClass);
610 MIB.addReg(ScratchReg,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp836 unsigned ScratchReg = 0; local
868 &ScratchReg, &TempReg);
872 SingleScratchReg = ScratchReg == TempReg;
987 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
1027 .addReg(ScratchReg, getKillRegState(true))
1055 // the negated frame size will be placed in ScratchReg.
1061 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
1066 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
1072 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
1073 .addReg(ScratchReg, RegStat
1405 unsigned ScratchReg = 0; local
[all...]
H A DPPCAsmPrinter.cpp396 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg(); local
400 .addReg(ScratchReg)
404 .addReg(ScratchReg)
405 .addReg(ScratchReg)
409 .addReg(ScratchReg)
410 .addReg(ScratchReg)
414 .addReg(ScratchReg)
415 .addReg(ScratchReg)
435 .addReg(ScratchReg));
438 .addReg(ScratchReg)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp305 Register ScratchReg = local
313 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
315 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
321 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
326 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
327 BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
328 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
332 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
H A DSystemZAsmPrinter.cpp633 unsigned ScratchReg = 0; local
636 ScratchReg = MI.getOperand(ScratchIdx).getReg();
637 } while (ScratchReg == SystemZ::R0D);
641 .addReg(ScratchReg)
646 .addReg(ScratchReg)
653 .addReg(ScratchReg));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp504 Register ScratchReg =
506 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset,
508 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
509 .addReg(ScratchReg)
510 .addReg(ScratchReg)
513 .ChangeToRegister(ScratchReg, false, false, true);
534 Register ScratchReg =
536 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
537 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
H A DAArch64FalkorHWPFFix.cpp751 for (unsigned ScratchReg : AArch64::GPR64RegClass) {
752 if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))
756 NewLdI.BaseReg = ScratchReg;
763 << printReg(ScratchReg, TRI) << '\n');
771 BuildMI(*MBB, &MI, DL, TII->get(AArch64::ORRXrs), ScratchReg)
776 BaseOpnd.setReg(ScratchReg);
782 << printReg(ScratchReg, TRI) << '\n');
784 ScratchReg); // Change tied operand pre/post update dest.
788 .addReg(ScratchReg)
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H A DAArch64AsmPrinter.cpp829 Register ScratchReg = MI.getOperand(1).getReg(); local
831 STI->getRegisterInfo()->getSubReg(ScratchReg, AArch64::sub_32);
860 .addReg(ScratchReg)
910 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg(); local
914 .addReg(ScratchReg)
918 .addReg(ScratchReg)
919 .addReg(ScratchReg)
923 .addReg(ScratchReg)
924 .addReg(ScratchReg)
927 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
1168 ScratchReg = MI->getOperand(1).getReg(), local
[all...]
H A DAArch64InstructionSelector.cpp2437 Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); local
2438 MIB.buildInstr(AArch64::JumpTableDest32, {TargetReg, ScratchReg},
H A DAArch64FastISel.cpp5132 const unsigned ScratchReg = createResultReg(&AArch64::GPR32RegClass); local
5137 .addDef(ScratchReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp807 unsigned ScratchReg = 0; local
822 ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
824 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
828 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
832 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
H A DThumb1FrameLowering.cpp71 unsigned ScratchReg, unsigned MIFlags) {
79 if (ScratchReg == ARM::NoRegister)
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
87 MRI.emitLoadConstPool(MBB, MBBI, dl, ScratchReg, 0, NumBytes, ARMCC::AL,
91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill)
67 emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned ScratchReg, unsigned MIFlags) argument
H A DARMAsmPrinter.cpp1977 Register ScratchReg = MI->getOperand(1).getReg();
1987 .addReg(ScratchReg)
2024 .addReg(ScratchReg)
2037 Register ScratchReg = MI->getOperand(1).getReg();
2040 .addReg(ScratchReg)
2051 .addReg(ScratchReg)
2057 .addReg(ScratchReg)
2093 .addReg(ScratchReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp2297 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true); local
2298 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2374 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2376 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2379 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2401 ScratchReg = X86::ESP;
2403 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2408 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2439 .addReg(ScratchReg)
2666 unsigned ScratchReg, SPRe
[all...]
H A DX86MCInstLower.cpp1393 Register ScratchReg = MI.getOperand(ScratchIdx).getReg(); local
1394 if (X86II::isX86_64ExtendedReg(ScratchReg))
1400 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1405 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));

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