Searched refs:ScheduledInstrs (Results 1 - 4 of 4) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h86 std::vector<MachineInstr *> ScheduledInstrs; member in class:llvm::ModuloSchedule
99 /// \arg ScheduledInstrs The new loop instructions, in total resequenced
101 /// \arg Cycle Cycle index for all instructions in ScheduledInstrs. Cycle does
102 /// not need to start at zero. ScheduledInstrs must be partially ordered by
106 std::vector<MachineInstr *> ScheduledInstrs,
109 : Loop(Loop), ScheduledInstrs(ScheduledInstrs), Cycle(std::move(Cycle)),
126 int getFirstCycle() { return Cycle[ScheduledInstrs.front()]; }
130 int getFinalCycle() { return Cycle[ScheduledInstrs.back()]; }
145 ArrayRef<MachineInstr *> getInstructions() { return ScheduledInstrs; }
105 ModuloSchedule(MachineFunction &MF, MachineLoop *Loop, std::vector<MachineInstr *> ScheduledInstrs, DenseMap<MachineInstr *, int> Cycle, DenseMap<MachineInstr *, int> Stage) argument
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H A DMachinePipeliner.h485 DenseMap<int, std::deque<SUnit *>> ScheduledInstrs; member in class:llvm::SMSchedule
513 ScheduledInstrs.clear();
576 return ScheduledInstrs[cycle];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2304 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[checkCycle];
2323 ScheduledInstrs[curCycle].push_back(SU);
2816 ScheduledInstrs[cycle + (stage * InitiationInterval)];
2820 ScheduledInstrs[cycle].push_front(*I);
2827 ScheduledInstrs.erase(cycle);
2839 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[Cycle];
2875 const_sched_iterator cycleInstrs = ScheduledInstrs.find(cycle);
H A DModuloSchedule.cpp26 for (MachineInstr *MI : ScheduledInstrs)

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