Searched refs:SUBE (Results 1 - 17 of 17) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h126 case ISD::SUBE:
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h233 ADDE, SUBE, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h107 SUBE, // Sub using carry
H A DARMISelLowering.cpp1587 case ARMISD::SUBE: return "ARMISD::SUBE";
6402 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
6410 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
8849 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
8857 Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0),
8862 // But the carry returned by ARMISD::SUBE is not a borrow as expected
11391 AddeSubeNode->getOpcode() == ARMISD::SUBE) &&
11392 "Expect an ADDE or SUBE");
11402 (AddeSubeNode->getOpcode() == ARMISD::SUBE
[all...]
H A DARMISelDAGToDAG.cpp3427 case ARMISD::SUBE: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp299 case ISD::SUBE: return "sube";
H A DLegalizeIntegerTypes.cpp149 case ISD::SUBE:
1101 // Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1102 // the third operand of ADDE/SUBE nodes is carry flag, which differs from
1902 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
2293 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2295 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2312 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2409 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
4025 // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
H A DDAGCombiner.cpp1522 case ISD::SUBE: return visitSUBE(N);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1551 setOperationAction(ISD::SUBE, MVT::i32, Custom);
1557 setOperationAction(ISD::SUBE, MVT::i64, Custom);
2906 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2907 case ISD::SUBE: hasChain = true; break;
3055 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp760 case ISD::SUBE: {
1003 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
H A DR600ISelLowering.cpp263 setOperationAction(ISD::SUBE, VT, Expand);
H A DAMDGPUISelLowering.cpp325 // AMDGPU uses ADDC/SUBC/ADDE/SUBE
329 setOperationAction(ISD::SUBE, VT, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp71 setOperationAction(ISD::SUBE, VT, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp677 // ADDC/ADDE/SUBC/SUBE default to expand.
681 setOperationAction(ISD::SUBE, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp115 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp338 setOperationAction(ISD::SUBE, MVT::i32, Custom);
342 setOperationAction(ISD::SUBE, MVT::i64, Custom);
2447 case ISD::SUBE:
3187 case ISD::SUBE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp207 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
213 setOperationAction(ISD::SUBE, VT, Legal);

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