Searched refs:STI (Results 1 - 25 of 435) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCParser/
H A DMCTargetAsmParser.cpp15 const MCSubtargetInfo &STI,
17 : MCOptions(MCOptions), STI(&STI), MII(MII) {}
23 STI = &STICopy;
28 return *STI;
14 MCTargetAsmParser(MCTargetOptions const &MCOptions, const MCSubtargetInfo &STI, const MCInstrInfo &MII) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O) override;
34 const MCSubtargetInfo &STI, raw_ostream &O);
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
39 const MCSubtargetInfo &STI,
44 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
48 const MCSubtargetInfo &STI, raw_ostream &O);
50 const MCSubtargetInfo &STI, raw_ostream &O);
53 const MCSubtargetInfo &STI, raw_ostream &O);
55 const MCSubtargetInfo &STI, raw_ostream &O);
57 const MCSubtargetInfo &STI, raw_ostrea
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H A DARMTargetStreamer.cpp119 static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) { argument
120 if (STI.getCPU() == "xscale")
123 if (STI.hasFeature(ARM::HasV8Ops)) {
124 if (STI.hasFeature(ARM::FeatureRClass))
127 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps))
129 else if (STI.hasFeature(ARM::HasV8MMainlineOps))
131 else if (STI.hasFeature(ARM::HasV7Ops)) {
132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
135 } else if (STI
153 isV8M(const MCSubtargetInfo &STI) argument
162 emitTargetAttributes(const MCSubtargetInfo &STI) argument
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H A DARMAsmBackend.h21 // The STI from the target triple the MCAsmBackend was instantiated with
22 // note that MCFragments may have a different local STI that should be
24 const MCSubtargetInfo &STI; member in class:llvm::ARMAsmBackend
27 ARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, argument
29 : MCAsmBackend(Endian), STI(STI),
30 isThumbMode(STI.getTargetTriple().isThumb()) {}
36 // FIXME: this should be calculated per fragment as the STI may be
38 bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; }
50 const MCSubtargetInfo *STI) cons
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H A DARMAsmBackendWinCOFF.h19 ARMAsmBackendWinCOFF(const Target &T, const MCSubtargetInfo &STI) argument
20 : ARMAsmBackend(T, STI, support::little) {}
H A DARMAsmBackendELF.h22 ARMAsmBackendELF(const Target &T, const MCSubtargetInfo &STI, uint8_t OSABI, argument
24 : ARMAsmBackend(T, STI, Endian), OSABI(OSABI) {}
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h35 bool isMicroMips(const MCSubtargetInfo &STI) const;
36 bool isMips32r6(const MCSubtargetInfo &STI) const;
47 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
52 const MCSubtargetInfo &STI) const override;
58 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
82 const MCSubtargetInfo &STI) const;
86 const MCSubtargetInfo &STI) cons
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.h28 const MCSubtargetInfo &STI, raw_ostream &O) override;
29 bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
31 bool isV9(const MCSubtargetInfo &STI) const;
35 const MCSubtargetInfo &STI, raw_ostream &O);
36 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
40 const MCSubtargetInfo &STI, raw_ostream &O);
43 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
45 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
47 void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
49 bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h29 const MCSubtargetInfo &STI, raw_ostream &O) override;
34 const MCSubtargetInfo &STI, raw_ostream &O);
35 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
39 const MCSubtargetInfo &STI,
50 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
53 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
55 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
64 const MCSubtargetInfo &STI, raw_ostream &O) {
69 const MCSubtargetInfo &STI, raw_ostrea
63 printPostIncOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) argument
89 printMemExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument
108 printUImm12Offset(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument
114 printAMIndexedWB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument
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H A DAArch64MCCodeEmitter.cpp58 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
90 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) const;
103 const MCSubtargetInfo &STI) const;
109 const MCSubtargetInfo &STI) const;
115 const MCSubtargetInfo &STI) cons
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.h40 const MCSubtargetInfo &STI) const;
43 const MCSubtargetInfo &STI) const;
46 const MCSubtargetInfo &STI) const;
49 const MCSubtargetInfo &STI) const;
52 const MCSubtargetInfo &STI) const;
55 const MCSubtargetInfo &STI) const;
58 const MCSubtargetInfo &STI) const;
61 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
67 const MCSubtargetInfo &STI) cons
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h47 const MCSubtargetInfo &STI) const;
53 const MCSubtargetInfo &STI) const;
58 const MCSubtargetInfo &STI) const;
63 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
80 const MCSubtargetInfo &STI) const;
85 const MCSubtargetInfo &STI) const;
88 const MCSubtargetInfo &STI) const;
96 const MCSubtargetInfo &STI) cons
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H A DAVRELFStreamer.h19 AVRELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.h31 const MCSubtargetInfo &STI, raw_ostream &O) override;
34 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
37 const MCSubtargetInfo &STI, raw_ostream &O);
39 const MCSubtargetInfo &STI, raw_ostream &O);
40 void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
43 const MCSubtargetInfo &STI, raw_ostream &O);
47 const MCSubtargetInfo &STI, raw_ostream &O);
48 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
52 const MCSubtargetInfo &STI, raw_ostream &O);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h27 const MCSubtargetInfo &STI, raw_ostream &O);
31 const MCSubtargetInfo &STI, raw_ostream &O) override;
37 const MCSubtargetInfo &STI, raw_ostream &O);
40 const MCSubtargetInfo &STI, raw_ostream &O);
45 const MCSubtargetInfo &STI, raw_ostream &O);
52 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
54 void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
57 void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
59 void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
62 const MCSubtargetInfo &STI, raw_ostrea
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H A DAMDGPUMCAsmInfo.cpp55 unsigned AMDGPUMCAsmInfo::getMaxInstLength(const MCSubtargetInfo *STI) const {
56 if (!STI || STI->getTargetTriple().getArch() == Triple::r600)
60 if (STI->getFeatureBits()[AMDGPU::FeatureNSAEncoding])
64 if (STI->getFeatureBits()[AMDGPU::FeatureVOP3Literal])
H A DAMDGPUMCCodeEmitter.h40 const MCSubtargetInfo &STI) const;
44 const MCSubtargetInfo &STI) const {
50 const MCSubtargetInfo &STI) const {
56 const MCSubtargetInfo &STI) const {
62 const MCSubtargetInfo &STI) const {
68 const MCSubtargetInfo &STI) const {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/InstPrinter/
H A DVEInstPrinter.cpp43 StringRef Annot, const MCSubtargetInfo &STI,
45 if (!printAliasInstr(MI, STI, OS))
46 printInstruction(MI, Address, STI, OS);
51 const MCSubtargetInfo &STI, raw_ostream &O) {
75 const MCSubtargetInfo &STI,
79 printOperand(MI, opNum, STI, O);
81 printOperand(MI, opNum + 1, STI, O);
87 printOperand(MI, opNum + 1, STI, O);
90 printOperand(MI, opNum, STI, O);
95 const MCSubtargetInfo &STI,
42 printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) argument
50 printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument
74 printMemASXOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) argument
94 printMemASOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) argument
114 printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstructionSelector.cpp34 const RISCVSubtarget &STI,
43 const RISCVSubtarget &STI; member in class:__anon2384::RISCVInstructionSelector
49 // uses "STI." in the code generated by TableGen. We need to unify the name of
51 const RISCVSubtarget *Subtarget = &STI;
69 const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
71 : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
72 TRI(*STI.getRegisterInfo()), RBI(RBI),
68 RISCVInstructionSelector( const RISCVTargetMachine &TM, const RISCVSubtarget &STI, const RISCVRegisterBankInfo &RBI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp49 const MCSubtargetInfo &STI) const override;
55 const MCSubtargetInfo &STI) const;
61 const MCSubtargetInfo &STI) const;
69 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
81 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
87 const MCSubtargetInfo &STI) cons
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCShuffler.h32 MCSubtargetInfo const &STI, MCInst &MCB)
33 : HexagonShuffler(Context, Fatal, MCII, STI) {
38 MCSubtargetInfo const &STI, MCInst &MCB,
40 : HexagonShuffler(Context, Fatal, MCII, STI) {
57 MCSubtargetInfo const &STI, MCInst &MCB);
59 MCSubtargetInfo const &STI, MCInst &MCB,
62 MCSubtargetInfo const &STI, MCInst &MCB,
31 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB) argument
37 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB, MCInst const &AddMI, bool InsertAtFront) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/
H A DCodeEmitter.cpp27 if (MAB.mayNeedRelaxation(Inst, STI))
28 MAB.relaxInstruction(Inst, STI, Relaxed);
31 MCE.encodeInstruction(Relaxed, VecOS, Fixups, STI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h68 /// Streams isa version string for given subtarget \p STI into \p Stream.
69 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
71 /// \returns True if given subtarget \p STI supports code object version 3,
73 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
75 /// \returns Wavefront size for given subtarget \p STI.
76 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
78 /// \returns Local memory size in bytes for given subtarget \p STI.
79 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
82 /// STI.
83 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
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H A DAMDGPUBaseInfo.cpp226 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) { argument
227 auto TargetTriple = STI->getTargetTriple();
228 auto Version = getIsaVersion(STI->getCPU());
239 if (hasXNACK(*STI))
241 if (hasSRAMECC(*STI))
247 bool hasCodeObjectV3(const MCSubtargetInfo *STI) { argument
248 return STI->getTargetTriple().getOS() == Triple::AMDHSA &&
249 STI->getFeatureBits().test(FeatureCodeObjectV3);
252 unsigned getWavefrontSize(const MCSubtargetInfo *STI) { argument
253 if (STI
261 getLocalMemorySize(const MCSubtargetInfo *STI) argument
270 getEUsPerCU(const MCSubtargetInfo *STI) argument
274 getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) argument
286 getMaxWavesPerCU(const MCSubtargetInfo *STI) argument
290 getMaxWavesPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) argument
295 getMinWavesPerEU(const MCSubtargetInfo *STI) argument
299 getMaxWavesPerEU(const MCSubtargetInfo *STI) argument
306 getMaxWavesPerEU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) argument
312 getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) argument
316 getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) argument
321 getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) argument
327 getSGPRAllocGranule(const MCSubtargetInfo *STI) argument
336 getSGPREncodingGranule(const MCSubtargetInfo *STI) argument
340 getTotalNumSGPRs(const MCSubtargetInfo *STI) argument
347 getAddressableNumSGPRs(const MCSubtargetInfo *STI) argument
359 getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) argument
376 getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable) argument
393 getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed) argument
417 getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed) argument
423 getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) argument
429 getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional<bool> EnableWavefrontSize32) argument
437 getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional<bool> EnableWavefrontSize32) argument
442 getTotalNumVGPRs(const MCSubtargetInfo *STI) argument
448 getAddressableNumVGPRs(const MCSubtargetInfo *STI) argument
452 getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) argument
463 getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) argument
472 getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional<bool> EnableWavefrontSize32) argument
482 initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI) argument
518 getDefaultAmdhsaKernelDescriptor( const MCSubtargetInfo *STI) argument
720 getLastSymbolicHwreg(const MCSubtargetInfo &STI) argument
729 isValidHwreg(int64_t Id, const MCSubtargetInfo &STI) argument
752 getHwreg(unsigned Id, const MCSubtargetInfo &STI) argument
782 isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict) argument
921 hasXNACK(const MCSubtargetInfo &STI) argument
925 hasSRAMECC(const MCSubtargetInfo &STI) argument
929 hasMIMG_R128(const MCSubtargetInfo &STI) argument
933 hasPackedD16(const MCSubtargetInfo &STI) argument
937 isSI(const MCSubtargetInfo &STI) argument
941 isCI(const MCSubtargetInfo &STI) argument
945 isVI(const MCSubtargetInfo &STI) argument
949 isGFX9(const MCSubtargetInfo &STI) argument
953 isGFX10(const MCSubtargetInfo &STI) argument
957 isGCN3Encoding(const MCSubtargetInfo &STI) argument
1023 getMCReg(unsigned Reg, const MCSubtargetInfo &STI) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.h21 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument
22 : MCDisassembler(STI, Ctx) {}

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