| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { argument
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { argument
154 if (!Register::isVirtualRegister(SReg))
155 return getDPRLaneFromSPR(SReg);
157 MachineInstr *MI = MRI->getVRegDef(SReg);
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
165 SReg
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 4867 unsigned SReg, unsigned &Lane) {
4868 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4875 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4866 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 134 /// records virtReg is a split live interval from SReg.
135 void setIsSplitFromReg(Register virtReg, unsigned SReg) { argument
136 Virt2SplitMap[virtReg.id()] = SReg;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LivePhysRegs.cpp | 263 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
264 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
|
| H A D | RegisterScavenging.cpp | 560 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI); local
563 if (!isRegUsed(SReg)) {
564 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
565 return SReg;
571 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
575 << printReg(SReg, TRI) << "\n");
577 return SReg;
668 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), local
670 MRI.replaceRegWith(VReg, SReg);
672 return SReg;
708 Register SReg = scavengeVReg(MRI, RS, Reg, true); local
734 Register SReg = scavengeVReg(MRI, RS, Reg, false); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInsertSkips.cpp | 382 unsigned SReg = AMDGPU::NoRegister; local
384 SReg = Op2.getReg();
388 if (M->definesRegister(SReg, TRI))
390 if (M->modifiesRegister(SReg, TRI))
392 ReadsSreg |= M->readsRegister(SReg, TRI);
412 if (SReg == ExecReg) {
|
| H A D | SIShrinkInstructions.cpp | 746 Register SReg = Src2->getReg(); local
747 if (Register::isVirtualRegister(SReg)) {
748 MRI.setRegAllocationHint(SReg, 0, VCCReg);
751 if (SReg != VCCReg)
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| H A D | SIInstrInfo.cpp | 834 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local
835 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
842 .addReg(SReg);
847 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local
849 : AMDGPU::S_CSELECT_B64), SReg)
857 .addReg(SReg);
861 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local
863 : AMDGPU::S_CSELECT_B64), SReg)
871 .addReg(SReg);
877 Register SReg local
891 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local
903 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local
921 Register SReg = MRI.createVirtualRegister(BoolXExecRC); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | MemRegion.h | 1159 const SubRegion *SReg)
1160 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) {
1165 bool IsVirtual, const MemRegion *SReg);
1196 CXXDerivedObjectRegion(const CXXRecordDecl *DerivedD, const SubRegion *SReg) argument
1197 : TypedValueRegion(SReg, CXXDerivedObjectRegionKind), DerivedD(DerivedD) {
1202 assert(SReg->getSymbolicBase() &&
1207 const MemRegion *SReg);
1158 CXXBaseObjectRegion(const CXXRecordDecl *RD, bool IsVirtual, const SubRegion *SReg) argument
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | MemRegion.cpp | 400 const MemRegion *SReg) {
403 ID.AddPointer(SReg);
412 const MemRegion *SReg) {
414 ID.AddPointer(SReg);
397 ProfileRegion(llvm::FoldingSetNodeID &ID, const CXXRecordDecl *RD, bool IsVirtual, const MemRegion *SReg) argument
410 ProfileRegion(llvm::FoldingSetNodeID &ID, const CXXRecordDecl *RD, const MemRegion *SReg) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 1126 SReg = MF.getRegInfo().createVirtualRegister(RC);
1130 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1135 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1161 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
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| H A D | PPCISelLowering.cpp | 10908 Register SReg = RegInfo.createVirtualRegister(GPRC); local
10909 BuildMI(BB, dl, TII->get(PPC::AND), SReg)
10912 unsigned ValueReg = SReg;
10917 .addReg(SReg)
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4751 unsigned SReg = Inst.getOperand(1).getReg(); local
4759 if (DReg == SReg) {
4767 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4772 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4798 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
4799 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4814 unsigned SReg = Inst.getOperand(1).getReg(); local
4826 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4831 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
4840 TOut.emitRRI(Mips::SRL, DReg, SReg,
4876 unsigned SReg = Inst.getOperand(1).getReg(); local
4939 unsigned SReg = Inst.getOperand(1).getReg(); local
[all...] |