Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 - 12 of 12) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h560 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
569 SIGN_EXTEND_VECTOR_INREG, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp67 case ISD::SIGN_EXTEND_VECTOR_INREG:
394 case ISD::SIGN_EXTEND_VECTOR_INREG:
860 case ISD::SIGN_EXTEND_VECTOR_INREG:
1979 case ISD::SIGN_EXTEND_VECTOR_INREG:
2786 case ISD::SIGN_EXTEND_VECTOR_INREG:
3253 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3362 case ISD::SIGN_EXTEND_VECTOR_INREG:
3378 case ISD::SIGN_EXTEND_VECTOR_INREG:
4317 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp);
H A DSelectionDAGDumper.cpp324 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
H A DLegalizeVectorOps.cpp117 /// Implement expansion for SIGN_EXTEND_VECTOR_INREG.
440 case ISD::SIGN_EXTEND_VECTOR_INREG:
854 case ISD::SIGN_EXTEND_VECTOR_INREG:
H A DTargetLowering.cpp1711 case ISD::SIGN_EXTEND_VECTOR_INREG: {
1716 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
2513 case ISD::SIGN_EXTEND_VECTOR_INREG:
H A DLegalizeIntegerTypes.cpp111 case ISD::SIGN_EXTEND_VECTOR_INREG:
4366 case ISD::SIGN_EXTEND_VECTOR_INREG:
H A DDAGCombiner.cpp1572 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
9090 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
9156 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
10607 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ||
10611 TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT))
10612 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT,
18947 Opcode != ISD::SIGN_EXTEND_VECTOR_INREG &&
H A DSelectionDAG.cpp3086 case ISD::SIGN_EXTEND_VECTOR_INREG: {
3639 case ISD::SIGN_EXTEND_VECTOR_INREG: {
4690 case ISD::SIGN_EXTEND_VECTOR_INREG:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp84 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
139 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1102 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);
1307 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1543 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
1800 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom);
2016 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
6011 case ISD::SIGN_EXTEND_VECTOR_INREG:
6012 return ISD::SIGN_EXTEND_VECTOR_INREG;
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp698 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp373 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
5197 case ISD::SIGN_EXTEND_VECTOR_INREG:
5510 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||

Completed in 380 milliseconds