Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 - 12 of 12) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 560 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 569 SIGN_EXTEND_VECTOR_INREG, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 67 case ISD::SIGN_EXTEND_VECTOR_INREG: 394 case ISD::SIGN_EXTEND_VECTOR_INREG: 860 case ISD::SIGN_EXTEND_VECTOR_INREG: 1979 case ISD::SIGN_EXTEND_VECTOR_INREG: 2786 case ISD::SIGN_EXTEND_VECTOR_INREG: 3253 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); 3362 case ISD::SIGN_EXTEND_VECTOR_INREG: 3378 case ISD::SIGN_EXTEND_VECTOR_INREG: 4317 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp);
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H A D | SelectionDAGDumper.cpp | 324 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
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H A D | LegalizeVectorOps.cpp | 117 /// Implement expansion for SIGN_EXTEND_VECTOR_INREG. 440 case ISD::SIGN_EXTEND_VECTOR_INREG: 854 case ISD::SIGN_EXTEND_VECTOR_INREG:
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H A D | TargetLowering.cpp | 1711 case ISD::SIGN_EXTEND_VECTOR_INREG: { 1716 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; 2513 case ISD::SIGN_EXTEND_VECTOR_INREG:
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H A D | LegalizeIntegerTypes.cpp | 111 case ISD::SIGN_EXTEND_VECTOR_INREG: 4366 case ISD::SIGN_EXTEND_VECTOR_INREG:
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H A D | DAGCombiner.cpp | 1572 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N); 9090 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || 9156 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) 10607 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || 10611 TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT)) 10612 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, 18947 Opcode != ISD::SIGN_EXTEND_VECTOR_INREG &&
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H A D | SelectionDAG.cpp | 3086 case ISD::SIGN_EXTEND_VECTOR_INREG: { 3639 case ISD::SIGN_EXTEND_VECTOR_INREG: { 4690 case ISD::SIGN_EXTEND_VECTOR_INREG:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 84 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); 139 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); 1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); 1019 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); 1102 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal); 1307 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); 1543 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); 1800 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom); 2016 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG); 6011 case ISD::SIGN_EXTEND_VECTOR_INREG: 6012 return ISD::SIGN_EXTEND_VECTOR_INREG; [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 698 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 373 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); 5197 case ISD::SIGN_EXTEND_VECTOR_INREG: 5510 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
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