Searched refs:SHL (Results 1 - 25 of 64) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h35 SHL = 0x17, enumerator in enum:llvm::LPAC::AluCode
92 case SHL:
112 .Case("sh", SHL)
134 case ISD::SHL:
135 return AluCode::SHL;
H A DLanaiISelLowering.cpp946 Res = DAG.getNode(ISD::SHL, DL, VT, V,
960 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
1240 assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1264 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1268 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1276 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1315 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
H A DLanaiMemAluCombiner.cpp220 return LPAC::SHL;
/freebsd-11-stable/usr.bin/xlint/lint1/
H A Dop.h79 SHL, enumerator in enum:__anon13873
H A Dtree.c131 { SHL, { 1,0,1,0,0,1,1,0,0,0,0,0,1,0,0,1,1,
614 if (mp->m_balance || (tflag && (op == SHL || op == SHR)))
646 case SHL:
812 if (op == SHL || op == SHR || op == SHLASS || op == SHRASS) {
967 case SHL:
973 * width of the right operand. For SHL this may result in
2490 * Create a node for operators SHL and SHR.
2809 case SHL:
3608 case SHL:
3944 case SHL
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h26 case ISD::SHL: return ARM_AM::lsl;
H A DARMISelLowering.cpp191 setOperationAction(ISD::SHL, VT, Custom);
262 setOperationAction(ISD::SHL, VT, Custom);
919 setTargetDAGCombine(ISD::SHL);
1081 setOperationAction(ISD::SHL, MVT::i64, Custom);
1459 setTargetDAGCombine(ISD::SHL);
1815 if (Op.getOpcode() != ISD::SHL)
3193 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3676 SDValue SHL = local
3677 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3679 DAG.getNode(ISD::OR, dl, VTy, SHL, DA
12127 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), local
12138 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), local
12151 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), local
12164 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), local
12235 SDValue SHL = OR->getOperand(1); local
13985 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp603 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
884 case ISD::SHL: return SelectSHL(N);
1046 if (T1.getOpcode() != ISD::SHL)
1071 SDValue NewShl = DAG.getNode(ISD::SHL, DL, VT, NewAdd, C);
1147 SDValue NewShl = DAG.getNode(ISD::SHL, dl, VT, NewSrl, DC);
1616 case ISD::SHL:
1725 /// Search for a SHL(x, [<=MaxAmount]) subtree in the queue, return the one of
1743 if (Val.getOpcode() != ISD::SHL ||
1810 if (Val.getOpcode() == ISD::SHL) {
1829 } else if (V.getOpcode() == ISD::SHL) {
2122 WeightedLeaf SHL = Leaves.findSHL(31); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand.
317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand.
332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
451 { ISD::SHL, MVT::v16i16, 1 }, // psllw.
466 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
467 { ISD::SHL, MVT::v4i32, 1 }, // pslld
468 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw
502 { ISD::SHL, MV
[all...]
H A DX86ISelDAGToDAG.cpp676 if (U->getOperand(0).getOpcode() == ISD::SHL &&
680 if (U->getOperand(1).getOpcode() == ISD::SHL &&
702 case ISD::SHL:
855 case ISD::SHL:
866 case ISD::SHL: NewOpc = X86ISD::VSHLV; break;
1652 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
1695 if (Shift.getOpcode() != ISD::SHL ||
1722 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
1832 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
1852 // "((X >> (SHIFT + C1)) & (MASK)) << C1". Everything before the SHL wil
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp172 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, local
174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp86 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
680 // 2. SHL by M-N
723 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
725 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
784 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
961 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1223 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1302 case ISD::SHL:
1458 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1907 case ISD::SHL
[all...]
H A DLegalizeVectorOps.cpp385 case ISD::SHL:
799 DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
818 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
1056 // Make sure that the SRA and SHL instructions are available.
1058 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
1068 SDValue Op = DAG.getNode(ISD::SHL, DL, VT, Node->getOperand(0), ShiftSz);
1127 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
1221 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
1238 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
1357 // Notice that we can also use SHL
[all...]
H A DLegalizeDAG.cpp809 ISD::SHL, dl, Hi.getValueType(), Hi,
838 ISD::SHL, dl, Hi.getValueType(), Hi,
1177 case ISD::SHL:
1552 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
2626 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2633 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2640 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2649 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2674 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2675 Tmp3 = DAG.getNode(ISD::SHL, d
[all...]
H A DDAGCombiner.cpp1546 case ISD::SHL: return visitSHL(N);
1668 case ISD::SHL:
2439 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2442 DAG.getNode(ISD::SHL, DL, VT,
3509 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3519 DAG.getNode(ISD::SHL, DL, VT, N0,
3549 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
3558 if (N0.getOpcode() == ISD::SHL &&
3561 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3572 if (N0.getOpcode() == ISD::SHL
[all...]
H A DTargetLowering.cpp1320 case ISD::SHL: {
1343 unsigned Opc = ISD::SHL;
1375 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1380 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1385 // Repeat the SHL optimization above in cases where an extension
1404 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA));
1442 if (Op0.getOpcode() == ISD::SHL) {
1453 Opc = ISD::SHL;
1619 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
1906 // Cannot eliminate/lower SHL fo
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator in enum:llvm::ISD::NodeType
542 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp241 case LPAC::SHL:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp814 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
816 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
818 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
849 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
850 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt);
1289 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1293 SDValue Mask = DAG.getNode(ISD::SHL, D
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp399 case ISD::SHL:
410 /// Determine whether it is worth it to fold SHL into the addressing
413 assert(V.getOpcode() == ISD::SHL && "invalid opcode");
442 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
448 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
450 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
690 if (N.getOpcode() == ISD::SHL) {
918 /// Check if the given SHL node (\p N), can be used to form an
923 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
980 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp506 setTargetDAGCombine(ISD::SHL);
823 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
889 And1.getOperand(0).getOpcode() == ISD::SHL) {
1175 case ISD::SHL:
2351 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2354 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2401 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2411 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2445 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2476 SDValue SllX = DAG.getNode(ISD::SHL, D
[all...]
H A DMipsSEISelLowering.cpp102 setTargetDAGCombine(ISD::SHL);
341 setOperationAction(ISD::SHL, Ty, Legal);
805 return DAG.getNode(ISD::SHL, DL, VT, X,
887 // the ISD::SRA and ISD::SHL nodes.
888 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
906 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
1039 case ISD::SHL:
1501 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1525 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1660 DAG.getNode(ISD::SHL, D
[all...]
H A DMipsISelLowering.h473 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
476 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
/freebsd-11-stable/crypto/openssl/crypto/sha/asm/
H A Dsha512-ppc.pl45 $SHL="sldi";
53 $SHL="slwi";
193 $SHL $num,$num,`log(16*$SZ)/log(2)`
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp101 setOperationAction(ISD::SHL, MVT::i32, Legal);
190 SDValue LS = DAG.getNode(ISD::SHL, dl, MVT::i32, Op0,

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