| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1292 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1346 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1355 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1364 Rt == Rt2)
1375 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1439 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1452 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1463 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1474 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1485 DecodeFPR32RegisterClass(Inst, Rt2, Add
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1985 unsigned Rt2 = Rt + 1; local
2009 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2013 if (Rt2 == 15)
2032 if (Rt2 == 15)
2038 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2042 if (writeback && (Rn == Rt || Rn == Rt2))
5448 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
5453 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Addres
5474 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
5531 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
5568 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
5637 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); local
5847 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); local
6423 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
6446 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 711 uint32_t Rt2 = Bits32(opcode, 14, 10); local
717 integer t2 = UInt(Rt2);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 3966 // the Rt == Rt2. All of those are undefined behaviour.
3974 unsigned Rt2 = Inst.getOperand(2).getReg(); local
3979 if (RI->isSubRegisterEq(Rn, Rt2))
3991 unsigned Rt2 = Inst.getOperand(1).getReg(); local
3992 if (Rt == Rt2)
3993 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4004 unsigned Rt2 = Inst.getOperand(2).getReg(); local
4005 if (Rt == Rt2)
4006 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4020 unsigned Rt2 local
4101 unsigned Rt2 = Inst.getOperand(2).getReg(); local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5628 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5632 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
6731 // We have to be careful to not emit an invalid Rt2 here, because the rest of
7135 unsigned Rt2 = MRI->getEncodingValue(Reg2); local
7137 // Rt2 must be Rt + 1 and Rt must be even.
7138 if (Rt + 1 != Rt2 || (Rt & 1)) {
7256 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); local
7269 // Rt2 must be Rt + 1.
7270 if (Rt2 != Rt + 1) {
7284 if (Rt2
[all...] |
| /freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 6254 // the intrinsic has 4 because Rt and Rt2
6267 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1);
6268 Rt2 = Builder.CreateTruncOrBitCast(Rt2, Int32Ty);
6270 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm});
|
| /freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 10688 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 =
10964 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 =
11201 uint32_t Rt2 = ReadCoreReg(t2, &success);
11210 if (!MemAWrite(context, address + 4, Rt2, addr_byte_size))
13134 "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
13137 "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
13181 "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
13184 "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
13669 "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"},
13729 "strd<c> <Rt>, <Rt2>, [<R
[all...] |