Searched refs:RegOp (Results 1 - 25 of 30) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFoldTables.h30 // Do not insert the reverse map (MemOp -> RegOp) into the table.
34 // Do not insert the forward map (RegOp -> MemOp) into the table.
44 // Used for RegOp->MemOp conversion. Encoded as Log2(Align) + 1 to allow 0
86 const X86MemoryFoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
90 const X86MemoryFoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
H A DX86MCInstLower.cpp351 unsigned RegOp = IsStore ? 0 : 5; local
354 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
363 unsigned Reg = Inst.getOperand(RegOp).getReg();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp214 const MCOperand &RegOp) {
215 assert(RegOp.isReg() && "Register operand expected");
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg());
240 const MCOperand &RegOp = MI->getOperand(OpNo); local
249 printMemoryBaseRegister(OS, AluCode, RegOp);
255 const MCOperand &RegOp = MI->getOperand(OpNo); local
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected.");
265 OS << "%" << getRegisterName(RegOp.getReg());
276 const MCOperand &RegOp = MI->getOperand(OpNo); local
285 printMemoryBaseRegister(OS, AluCode, RegOp);
213 printMemoryBaseRegister(raw_ostream &OS, const unsigned AluCode, const MCOperand &RegOp) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp67 const MCOperand &RegOp = MI->getOperand(OpNo); local
71 assert(RegOp.isReg() && "Register operand not a register");
72 O << getRegisterName(RegOp.getReg());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRAsmPrinter.cpp96 const MachineOperand &RegOp = MI->getOperand(OpNum); local
98 assert(RegOp.isReg() && "Operand must be a register when you're"
100 Register Reg = RegOp.getReg();
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h495 /// Get all register state flags from machine operand \p RegOp.
496 inline unsigned getRegState(const MachineOperand &RegOp) { argument
497 assert(RegOp.isReg() && "Not a register operand");
498 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
499 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
500 getUndefRegState(RegOp.isUndef()) |
501 getInternalReadRegState(RegOp.isInternalRead()) |
502 getDebugRegState(RegOp
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAsmPrinter.cpp130 unsigned RegOp = OpNo + 1; local
131 if (RegOp >= MI->getNumOperands())
133 const MachineOperand &MO = MI->getOperand(RegOp);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp137 auto RegOp = MI.getOperand(OpNo); local
140 assert(RegOp.isReg() && "Expected register operand");
144 switch (RegOp.getReg()) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp586 unsigned RegOp = OpNum; local
592 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
595 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
598 RegOp = OpNum + 1;
600 if (RegOp >= MI->getNumOperands())
602 const MachineOperand &MO = MI->getOperand(RegOp);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1388 const MachineOperand *RegOp = nullptr; local
1394 RegOp = Src1;
1397 RegOp = Src0;
1409 return std::make_pair(RegOp, OMod);
1439 const MachineOperand *RegOp; local
1441 std::tie(RegOp, OMod) = isOMod(MI);
1442 if (OMod == SIOutMods::NONE || !RegOp->isReg() ||
1443 RegOp->getSubReg() != AMDGPU::NoSubRegister ||
1444 !hasOneNonDBGUseInst(*MRI, RegOp->getReg()))
1447 MachineInstr *Def = MRI->getVRegDef(RegOp
[all...]
H A DSIInstrInfo.cpp875 MachineOperand RegOp = Cond[1]; local
876 RegOp.setImplicit(false);
879 .add(RegOp);
889 MachineOperand RegOp = Cond[1]; local
890 RegOp.setImplicit(false);
893 .add(RegOp);
1652 MachineOperand &RegOp,
1654 Register Reg = RegOp.getReg();
1655 unsigned SubReg = RegOp.getSubReg();
1656 bool IsKill = RegOp
1651 swapRegAndNonRegOperand(MachineInstr &MI, MachineOperand &RegOp, MachineOperand &NonRegOp) argument
[all...]
H A DGCNHazardRecognizer.cpp126 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, local
128 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_;
H A DAMDGPUMachineCFGStructurizer.cpp1882 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
1883 ArrayRef<MachineOperand> Cond(RegOp);
2341 MachineOperand RegOp =
2343 ArrayRef<MachineOperand> Cond(RegOp);
2400 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2401 ArrayRef<MachineOperand> Cond(RegOp);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp87 struct RegOp { struct in struct:__anon2197::BPFOperand
98 RegOp Reg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h46 struct RegOp { struct in struct:llvm::final
75 struct RegOp Reg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1606 unsigned RegOp = CurOp++;
1613 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),
1619 unsigned RegOp = CurOp++;
1623 emitRegModRMByte(MI.getOperand(RegOp), 0, CurByte, OS);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp358 MachineOperand &RegOp = PI.getOperand(i); local
359 if (RegOp.getSubReg() == 0)
369 .addReg(RegOp.getReg(), getRegState(RegOp),
370 RegOp.getSubReg());
372 RegOp.setReg(NewReg);
373 RegOp.setSubReg(0);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp120 struct RegOp { struct in struct:__anon2281::LanaiOperand
137 struct RegOp Reg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp629 MachineOperand &RegOp = I.getOperand(1); local
630 RegOp.setReg(SubRegCopy.getReg(0));
758 MachineOperand &RegOp = I.getOperand(1); local
759 RegOp.setReg(PromoteReg);
1649 MachineOperand &RegOp = I.getOperand(0); local
1650 RegOp.setReg(DefGPRReg);
4032 MachineOperand &RegOp = I.getOperand(1); local
4033 RegOp.setReg(Reg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp230 struct RegOp { struct in class:__anon2392::SparcOperand
247 struct RegOp Reg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp388 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; local
389 if (RegOp >= MI->getNumOperands())
391 const MachineOperand &MO = MI->getOperand(RegOp);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp226 struct RegOp { struct in struct:__anon2376::RISCVOperand
245 RegOp Reg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp105 struct RegOp { struct in class:__anon2401::SystemZOperand
135 RegOp Reg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1760 const MachineOperand &RegOp = MI.getOperand(IsAddi ? 1 : 2); local
1762 assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp1336 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode()))
1337 return RegOp->getRegMask();

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