Searched refs:Reg (Results 1 - 25 of 537) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegister.h20 unsigned Reg; member in class:llvm::Register
23 Register(unsigned Val = 0): Reg(Val) {}
24 Register(MCRegister Val): Reg(Val) {}
39 /// returns true if Reg is in the range used for stack slots.
45 static bool isStackSlot(unsigned Reg) { argument
46 return MCRegister::isStackSlot(Reg);
50 static int stackSlot2Index(unsigned Reg) { argument
51 assert(isStackSlot(Reg) && "Not a stack slot");
52 return int(Reg - (1u << 30));
63 static bool isPhysicalRegister(unsigned Reg) { argument
69 isVirtualRegister(unsigned Reg) argument
76 virtReg2Index(unsigned Reg) argument
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H A DLiveRegUnits.h56 Register Reg = O->getReg(); local
57 if (!Reg.isPhysical())
63 if (!TRI->isConstantPhysReg(Reg))
64 ModifiedRegUnits.addReg(Reg);
66 assert(O->isUse() && "Reg operand not a def and not a use");
67 UsedRegUnits.addReg(Reg);
86 /// Adds register units covered by physical register \p Reg.
87 void addReg(MCPhysReg Reg) { argument
88 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
92 /// Adds register units covered by physical register \p Reg tha
94 addRegMasked(MCPhysReg Reg, LaneBitmask Mask) argument
103 removeReg(MCPhysReg Reg) argument
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H A DLiveVariables.h105 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
106 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
109 unsigned Reg,
149 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
152 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
157 void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
158 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
164 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
169 MachineInstr *FindLastPartialDef(unsigned Reg,
283 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
301 isPHIJoin(unsigned Reg) argument
304 setPHIJoin(unsigned Reg) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegister.h23 unsigned Reg; member in class:llvm::MCRegister
26 MCRegister(unsigned Val = 0): Reg(Val) {}
46 static bool isStackSlot(unsigned Reg) { argument
47 return int(Reg) >= (1 << 30);
52 static bool isPhysicalRegister(unsigned Reg) { argument
53 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
54 return int(Reg) > 0;
60 return isPhysicalRegister(Reg);
64 return Reg;
68 return Reg;
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H A DMCWin64EH.h26 static WinEH::Instruction PushNonVol(MCSymbol *L, unsigned Reg) { argument
27 return WinEH::Instruction(Win64EH::UOP_PushNonVol, L, Reg, -1);
36 static WinEH::Instruction SaveNonVol(MCSymbol *L, unsigned Reg, argument
40 L, Reg, Offset);
42 static WinEH::Instruction SaveXMM(MCSymbol *L, unsigned Reg, argument
46 L, Reg, Offset);
48 static WinEH::Instruction SetFPReg(MCSymbol *L, unsigned Reg, unsigned Off) { argument
49 return WinEH::Instruction(UOP_SetFPReg, L, Reg, Off);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64TargetStreamer.h42 virtual void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) {} argument
43 virtual void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} argument
44 virtual void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} argument
45 virtual void EmitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} argument
46 virtual void EmitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} argument
47 virtual void EmitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} argument
48 virtual void EmitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} argument
49 virtual void EmitARM64WinCFISaveFRegPX(unsigned Reg, int Offset) {} argument
87 void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) override;
88 void EmitARM64WinCFISaveRegX(unsigned Reg, in
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MachineFunctionInfo.cpp24 unsigned Reg = *CSR; ++CSR) {
25 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h42 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
48 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h61 unsigned getFirstReg(unsigned Reg);
64 inline unsigned getRegAsGR64(unsigned Reg) { argument
65 return GR64Regs[getFirstReg(Reg)];
69 inline unsigned getRegAsGR32(unsigned Reg) { argument
70 return GR32Regs[getFirstReg(Reg)];
74 inline unsigned getRegAsGRH32(unsigned Reg) { argument
75 return GRH32Regs[getFirstReg(Reg)];
79 inline unsigned getRegAsVR128(unsigned Reg) { argument
80 return VR128Regs[getFirstReg(Reg)];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
60 VRegInfo[Reg].first = RC;
63 void MachineRegisterInfo::setRegBank(unsigned Reg, argument
65 VRegInfo[Reg].first = &RegBank;
69 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, argument
80 MRI.setRegClass(Reg, NewRC);
85 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
92 MachineRegisterInfo::constrainRegAttrs(unsigned Reg, argument
122 recomputeRegClass(unsigned Reg) argument
147 unsigned Reg = Register::index2VirtReg(getNumVirtRegs()); local
165 unsigned Reg = createIncompleteVirtualRegister(Name); local
174 unsigned Reg = createIncompleteVirtualRegister(Name); local
190 unsigned Reg = createIncompleteVirtualRegister(Name); local
205 unsigned Reg = Register::index2VirtReg(i); local
613 disableCalleeSavedRegister(unsigned Reg) argument
663 unsigned Reg = *Super; local
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H A DAggressiveAntiDepBreaker.cpp75 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
76 unsigned Node = GroupNodeIndices[Reg];
88 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
89 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
90 Regs.push_back(Reg);
96 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
109 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { argument
119 IsLive(unsigned Reg) argument
165 unsigned Reg = *AI; local
179 unsigned Reg = *I; local
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H A DMachineInstrBundle.cpp158 Register Reg = MO.getReg(); local
159 if (!Reg)
162 if (LocalDefSet.count(Reg)) {
166 KilledDefSet.insert(Reg);
168 if (ExternUseSet.insert(Reg).second) {
169 ExternUses.push_back(Reg);
171 UndefUseSet.insert(Reg);
175 KilledUseSet.insert(Reg);
181 Register Reg = MO.getReg(); local
182 if (!Reg)
212 unsigned Reg = LocalDefs[i]; local
222 unsigned Reg = ExternUses[i]; local
281 AnalyzeVirtRegInBundle( MachineInstr &MI, unsigned Reg, SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops) argument
311 AnalyzePhysRegInBundle(const MachineInstr &MI, unsigned Reg, const TargetRegisterInfo *TRI) argument
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H A DMIRVRegNamerUtils.h33 Register Reg; member in class:llvm::VRegRenamer::NamedVReg
37 NamedVReg(Register Reg, std::string Name = "") : Reg(Reg), Name(Name) {} argument
38 NamedVReg(std::string Name = "") : Reg(~0U), Name(Name) {}
42 Register getReg() const { return Reg; }
H A DLivePhysRegs.cpp85 Register Reg = O->getReg(); local
86 if (!Register::isPhysicalRegister(Reg))
91 Clobbers.push_back(std::make_pair(Reg, &*O));
96 removeReg(Reg);
103 for (auto Reg : Clobbers) {
106 if (Reg.second->isReg() && Reg.second->isDead())
108 if (Reg.second->isRegMask() &&
109 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg
155 MCPhysReg Reg = LI.PhysReg; local
291 Register Reg = MO->getReg(); local
308 Register Reg = MO->getReg(); local
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H A DCriticalAntiDepBreaker.cpp75 unsigned Reg = *AI; local
76 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
77 KillIndices[Reg] = BBSize;
78 DefIndices[Reg] = ~0u;
89 unsigned Reg = *I; local
90 if (!IsReturnBlock && !Pristine.test(Reg))
93 unsigned Reg = *AI; local
94 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
95 KillIndices[Reg] = BBSize;
96 DefIndices[Reg]
190 Register Reg = MO.getReg(); local
285 Register Reg = MO.getReg(); local
316 Register Reg = MO.getReg(); local
626 Register Reg = MO.getReg(); local
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H A DRDFRegisters.cpp49 if (UnitInfos[U].Reg != 0)
57 UnitInfos[U].Reg = F;
62 UI.Reg = F;
101 std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
104 assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg));
105 if (isRegMaskId(Reg)) {
107 const uint32_t *MB = getRegMaskBits(Reg);
115 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRe
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp73 static bool isVecReg(unsigned Reg) { argument
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
75 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15)
76 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
95 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, argument
99 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);
107 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { argument
143 unsigned Reg = 0; local
151 unsigned Reg = 0; local
167 unsigned Reg = 0; local
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/freebsd-11-stable/sys/contrib/dev/acpica/components/hardware/
H A Dhwregs.c168 ACPI_GENERIC_ADDRESS *Reg,
191 * Reg - GAS register structure
203 ACPI_GENERIC_ADDRESS *Reg,
223 if (!Reg->BitOffset && Reg->BitWidth &&
224 ACPI_IS_POWER_OF_TWO (Reg->BitWidth) &&
225 ACPI_IS_ALIGNED (Reg->BitWidth, 8))
227 AccessBitWidth = Reg->BitWidth;
229 else if (Reg->AccessWidth)
231 AccessBitWidth = ACPI_ACCESS_BIT_WIDTH (Reg
201 AcpiHwGetAccessBitWidth( UINT64 Address, ACPI_GENERIC_ADDRESS *Reg, UINT8 MaxBitWidth) argument
287 AcpiHwValidateRegister( ACPI_GENERIC_ADDRESS *Reg, UINT8 MaxBitWidth, UINT64 *Address) argument
367 AcpiHwRead( UINT64 *Value, ACPI_GENERIC_ADDRESS *Reg) argument
465 AcpiHwWrite( UINT64 Value, ACPI_GENERIC_ADDRESS *Reg) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp44 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, argument
48 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
53 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, argument
57 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
62 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
64 return hasImplicitDefOfPhysReg(Reg, &RI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.h34 unsigned getHWRegIndex(unsigned Reg) const;
43 // \returns true if \p Reg can be defined in one ALU clause and used in
45 bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
51 void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
H A DAMDGPURegisterInfo.h33 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
H A DAMDGPUGlobalISelUtils.h24 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg);
H A DGCNRegBankReassign.cpp78 : Reg(r), SubReg(s), Mask(m) {}
79 unsigned Reg; member in class:__anon2099::GCNRegBankReassign::OperandMask
88 : MI(mi), Reg(reg), FreeBanks(freebanks), Weight(weight) {}
95 dbgs() << P->printReg(Reg) << " to banks ";
102 unsigned Reg; member in class:__anon2099::GCNRegBankReassign::Candidate
165 unsigned getPhysRegBank(unsigned Reg) const;
170 // If Bank is not -1 assume Reg:SubReg to belong to that Bank.
171 unsigned getRegBankMask(unsigned Reg, unsigned SubReg, int Bank);
175 // If Reg and Bank provided substitute the Reg wit
232 printReg(unsigned Reg, unsigned SubReg = 0) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMachineFunctionInfo.h47 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.h32 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
57 int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; }
69 int getISRRegFI(unsigned Reg) const { return ISRDataRegFI[Reg]; }

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