Searched refs:RO (Results 1 - 23 of 23) sorted by relevance

/freebsd-11-stable/contrib/ntp/libparse/
H A Dinfo_trimble.c56 { CMD_RDATAA, "CMD_RDATAA", "data channel A configuration (0x3D)", "trimble_channelA", RO },
57 { CMD_RALMANAC, "CMD_RALMANAC", "almanac data for sat (0x40)", "gps_almanac", RO },
58 { CMD_RCURTIME, "CMD_RCURTIME", "GPS time (0x41)", "gps_time", RO },
59 { CMD_RSPOSXYZ, "CMD_RSPOSXYZ", "single precision XYZ position (0x42)", "gps_position(XYZ)", RO|DEF },
60 { CMD_RVELOXYZ, "CMD_RVELOXYZ", "velocity fix (XYZ ECEF) (0x43)", "gps_velocity(XYZ)", RO|DEF },
61 { CMD_RBEST4, "CMD_RBEST4", "best 4 satellite selection (0x44)", "trimble_best4", RO|DEF },
62 { CMD_RVERSION, "CMD_RVERSION", "software version (0x45)", "trimble_version", RO|DEF },
63 { CMD_RRECVHEALTH, "CMD_RRECVHEALTH", "receiver health (0x46)", "trimble_receiver_health", RO|DEF },
64 { CMD_RSIGNALLV, "CMD_RSIGNALLV", "signal levels of all satellites (0x47)", "trimble_signal_levels", RO },
65 { CMD_RMESSAGE, "CMD_RMESSAGE", "GPS system message (0x48)", "gps-message", RO|DE
[all...]
/freebsd-11-stable/contrib/ntp/ntpd/
H A Dntp_control.c342 { CS_STRATUM, RO, "stratum" }, /* 2 */
343 { CS_PRECISION, RO, "precision" }, /* 3 */
344 { CS_ROOTDELAY, RO, "rootdelay" }, /* 4 */
345 { CS_ROOTDISPERSION, RO, "rootdisp" }, /* 5 */
346 { CS_REFID, RO, "refid" }, /* 6 */
347 { CS_REFTIME, RO, "reftime" }, /* 7 */
348 { CS_POLL, RO, "tc" }, /* 8 */
349 { CS_PEERID, RO, "peer" }, /* 9 */
350 { CS_OFFSET, RO, "offset" }, /* 10 */
351 { CS_DRIFT, RO, "frequenc
[all...]
H A Drefclock_neoclock4x.c738 tt = add_var(&out->kv_list, sizeof(tmpbuf)-1, RO|DEF);
741 tt = add_var(&out->kv_list, 40, RO|DEF);
743 tt = add_var(&out->kv_list, 40, RO|DEF);
745 tt = add_var(&out->kv_list, 40, RO|DEF);
747 tt = add_var(&out->kv_list, 40, RO|DEF);
754 tt = add_var(&out->kv_list, 40, RO|DEF);
761 tt = add_var(&out->kv_list, 40, RO|DEF);
768 tt = add_var(&out->kv_list, 80, RO|DEF);
770 tt = add_var(&out->kv_list, 40, RO|DEF);
772 tt = add_var(&out->kv_list, 80, RO|DE
[all...]
H A Drefclock_parse.c3559 tt = add_var(&out->kv_list, 80, RO);
3566 tt = add_var(&out->kv_list, 80, RO|DEF);
3570 start = tt = add_var(&out->kv_list, 128, RO|DEF);
3590 start = tt = add_var(&out->kv_list, 512, RO|DEF);
3624 start = tt = add_var(&out->kv_list, 80, RO|DEF);
3641 start = tt = add_var(&out->kv_list, LEN_STATES, RO|DEF);
3685 tt = add_var(&out->kv_list, 32, RO);
3688 tt = add_var(&out->kv_list, 80, RO);
3691 tt = add_var(&out->kv_list, 128, RO);
4346 set_var(&parse->kv, buffer, strlen(buffer)+1, RO|DE
[all...]
H A Dntp_config.c4969 set_sys_var(line, strlen(line) + 1, RO);
5122 set_sys_var(line, strlen(line) + 1, RO);
/freebsd-11-stable/sys/dev/aic7xxx/aicasm/
H A Daicasm_symbol.h65 RO = 0x01, enumerator in enum:__anon2
H A Daicasm_scan.l171 RW|RO|WO {
174 else if (strcmp(yytext, "RO") == 0)
175 yylval.value = RO;
H A Daicasm_gram.y1806 if (symbol->info.rinfo->mode == RO) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp820 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); local
822 SR = RO.getReg(), SSR = RO.getSubReg();
824 TR = RO.getReg(), TSR = RO.getSubReg();
826 FR = RO.getReg(), FSR = RO.getSubReg();
H A DHexagonGenInsert.cpp387 OrderedRegisterList(const RegisterOrdering &RO) argument
388 : MaxSize(MaxORLSize), Ord(RO) {}
529 void buildOrderingMF(RegisterOrdering &RO) const;
530 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
597 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
617 RO.insert(std::make_pair(R, Index++));
628 RegisterOrdering &RO) const {
642 RO.insert(std::make_pair(VRs[i], i));
H A DHexagonExpandCondsets.cpp228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
905 /// In the range [First, Last], rename all references to the "old" register RO
908 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, argument
922 if (!Op.isReg() || RO != RegisterRef(Op))
H A DHexagonInstrInfo.cpp644 const MachineOperand &RO = Cond[1]; local
645 unsigned Flags = getUndefRegState(RO.isUndef());
646 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
668 const MachineOperand &RO = Cond[1]; local
669 unsigned Flags = getUndefRegState(RO.isUndef());
670 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86WinCOFFTargetStreamer.cpp351 for (RegSaveOffset RO : RegSaveOffsets)
352 FuncOS << printFPOReg(MRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCodeGenFunction.cpp2355 CodeGenFunction::FormResolverCondition(const MultiVersionResolverOption &RO) {
2358 if (!RO.Conditions.Architecture.empty())
2359 Condition = EmitX86CpuIs(RO.Conditions.Architecture);
2361 if (!RO.Conditions.Features.empty()) {
2362 llvm::Value *FeatureCond = EmitX86CpuSupports(RO.Conditions.Features);
2404 for (const MultiVersionResolverOption &RO : Options) {
2406 llvm::Value *Condition = FormResolverCondition(RO);
2410 assert(&RO == Options.end() - 1 &&
2412 CreateMultiVersionResolverReturn(CGM, Resolver, Builder, RO.Function,
2419 CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder, RO
[all...]
H A DCodeGenModule.cpp2878 const CodeGenFunction::MultiVersionResolverOption &RO) {
2880 for (StringRef Feat : RO.Conditions.Features)
2883 if (!RO.Conditions.Architecture.empty())
2885 Priority, TI.multiVersionSortPriority(RO.Conditions.Architecture));
2877 TargetMVPriority(const TargetInfo &TI, const CodeGenFunction::MultiVersionResolverOption &RO) argument
H A DCodeGenFunction.h4390 llvm::Value *FormResolverCondition(const MultiVersionResolverOption &RO);
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DAsmWriterEmitter.cpp847 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; local
849 switch (RO.Kind) {
851 const Record *Rec = RO.getRecord();
852 StringRef ROName = RO.getName();
928 MIOpNum += RO.getMINumOperands();
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DRegionStore.cpp116 const RegionOffset &RO = R->getAsOffset(); local
117 if (RO.hasSymbolicOffset())
118 return BindingKey(cast<SubRegion>(R), cast<SubRegion>(RO.getRegion()), k);
120 return BindingKey(RO.getRegion(), RO.getOffset(), k);
1195 const RegionOffset &RO = baseR->getAsOffset(); local
1197 if (RO.hasSymbolicOffset()) {
1205 uint64_t LowerOffset = RO.getOffset();
/freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-diff/
H A DDifferenceEngine.cpp371 Value *LO = L->getOperand(I), *RO = R->getOperand(I); local
372 if (!equivalentAsOperands(LO, RO)) {
373 if (Complain) Engine.logf("operands %l and %r differ") << LO << RO; local
/freebsd-11-stable/contrib/ntp/include/
H A Dntpd.h93 #define RO (CAN_READ) macro
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/
H A DCompileOnDemandLayer.h193 using RO = ResourceOwnerImpl<ResourceT, ResourcePtrT>;
194 return std::make_unique<RO>(std::move(ResourcePtr));
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DModuleSummaryIndex.h781 void setReadOnly(bool RO) { VarFlags.MaybeReadOnly = RO; } argument
/freebsd-11-stable/contrib/netbsd-tests/usr.bin/netpgpverify/
H A Dt_netpgpverify.sh4526 WzXeEoo3yBp0wTl/qdjNs6m9XSxdnyHQ096Ei5oLc4lboZKC3lfh0Mc1fFVPp/RO

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