Searched refs:RISCV (Results 1 - 25 of 33) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
42 case RISCV::fixup_riscv_got_hi20:
43 case RISCV::fixup_riscv_tls_got_hi20:
44 case RISCV::fixup_riscv_tls_gd_hi20:
48 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
68 case RISCV::fixup_riscv_rvc_branch:
72 case RISCV::fixup_riscv_rvc_jump:
86 case RISCV::C_BEQZ:
88 Res.setOpcode(RISCV::BEQ);
90 Res.addOperand(MCOperand::createReg(RISCV
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H A DRISCVELFObjectWriter.cpp1 //===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
63 case RISCV::fixup_riscv_pcrel_hi20:
65 case RISCV::fixup_riscv_pcrel_lo12_i:
67 case RISCV::fixup_riscv_pcrel_lo12_s:
69 case RISCV::fixup_riscv_got_hi20:
71 case RISCV::fixup_riscv_tls_got_hi20:
73 case RISCV::fixup_riscv_tls_gd_hi20:
75 case RISCV::fixup_riscv_jal:
77 case RISCV::fixup_riscv_branch:
79 case RISCV
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H A DRISCVFixupKinds.h1 //===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===//
14 #undef RISCV macro
17 namespace RISCV { namespace in namespace:llvm
89 } // end namespace RISCV
H A DRISCVMCCodeEmitter.cpp1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
94 // and JALR won't go through RISCV MC to MC compressed instruction
105 if (MI.getOpcode() == RISCV::PseudoTAIL) {
107 Ra = RISCV::X6;
108 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
113 Ra = RISCV::X1;
122 TmpInst = MCInstBuilder(RISCV::AUIPC)
128 if (MI.getOpcode() == RISCV::PseudoTAIL)
130 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV
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H A DRISCVMCExpr.cpp1 //===-- RISCVMCExpr.cpp - RISCV specific MC expression classes ------------===//
10 // accepted by the RISCV architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
16 #include "RISCV.h"
80 case RISCV::fixup_riscv_got_hi20:
81 case RISCV::fixup_riscv_tls_got_hi20:
82 case RISCV::fixup_riscv_tls_gd_hi20:
83 case RISCV::fixup_riscv_pcrel_hi20:
H A DRISCVMCTargetDesc.cpp1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
9 /// This file provides RISCV-specific target descriptions.
49 InitRISCVMCRegisterInfo(X, RISCV::X1);
58 Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
H A DRISCVAsmBackend.h1 //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===//
49 return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax];
97 return RISCV::NumTargetFixupKinds;
131 static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
H A DRISCVELFStreamer.cpp1 //===-- RISCVELFStreamer.cpp - RISCV ELF Target Streamer Methods ----------===//
9 // This file provides RISCV specific target streamer methods.
34 if (Features[RISCV::FeatureStdExtC])
H A DRISCVInstPrinter.cpp1 //===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===//
9 // This class prints an RISCV MCInst to a .s file.
154 return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
155 : RISCV::ABIRegAltName);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
14 #include "RISCV.h"
29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
31 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
32 static_assert(RISCV
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H A DRISCVISelDAGToDAG.cpp1 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
9 // This file defines an instruction selector for the RISCV target.
14 #include "RISCV.h"
26 // RISCV-specific code to select RISCV machine instructions for
37 return "RISCV DAG->DAG Pattern Instruction Selection";
72 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
75 if (Inst.Opc == RISCV::LUI)
76 Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
118 RISCV
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H A DRISCVMergeBaseOffset.cpp26 #include "RISCV.h"
36 #define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
82 if (HiLUI.getOpcode() != RISCV::LUI ||
90 if (LoADDI->getOpcode() != RISCV::ADDI ||
137 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!");
147 if (OffsetTail.getOpcode() == RISCV::ADDI) {
157 if (OffsetLui.getOpcode() != RISCV::LUI ||
168 } else if (OffsetTail.getOpcode() == RISCV::LUI) {
190 case RISCV::ADDI: {
197 case RISCV
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H A DRISCVInstrInfo.cpp1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
14 #include "RISCV.h"
36 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
44 case RISCV::LB:
45 case RISCV::LBU:
46 case RISCV::LH:
47 case RISCV::LHU:
48 case RISCV
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H A DRISCVExpandPseudoInsts.cpp15 #include "RISCV.h"
25 #define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
102 case RISCV::PseudoAtomicLoadNand32:
105 case RISCV::PseudoAtomicLoadNand64:
108 case RISCV::PseudoMaskedAtomicSwap32:
111 case RISCV::PseudoMaskedAtomicLoadAdd32:
113 case RISCV::PseudoMaskedAtomicLoadSub32:
115 case RISCV::PseudoMaskedAtomicLoadNand32:
118 case RISCV::PseudoMaskedAtomicLoadMax32:
121 case RISCV
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H A DRISCVISelLowering.cpp1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
15 #include "RISCV.h"
83 addRegisterClass(XLenVT, &RISCV::GPRRegClass);
86 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
88 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
93 setStackPointerRegisterToSaveRestore(RISCV::X2);
377 return RISCV::BEQ;
379 return RISCV::BNE;
381 return RISCV
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H A DRISCVFrameLowering.cpp1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
9 // This file contains the RISCV implementation of TargetFrameLowering class.
81 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
86 unsigned Opc = RISCV::ADD;
90 Opc = RISCV::SUB;
93 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
103 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
106 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
218 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
224 MF.getRegInfo().createVirtualRegister(&RISCV
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H A DRISCVCallLowering.cpp28 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
H A DRISCVRegisterInfo.h1 //===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===//
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
61 return &RISCV::GPRRegClass;
H A DRISCVSubtarget.cpp1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
14 #include "RISCV.h"
53 UserReservedRegister(RISCV::NUM_TARGET_REGS),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Utils/
H A DRISCVMatInt.cpp32 Res.push_back(Inst(RISCV::LUI, Hi20));
35 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
73 Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
75 Res.push_back(Inst(RISCV::ADDI, Lo12));
H A DRISCVBaseInfo.cpp17 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
68 Register getBPReg() { return RISCV::X9; }
75 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
57 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
58 bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); }
200 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) {
205 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) {
282 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
771 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
772 return Reg - RISCV::F0_D + RISCV
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
66 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
71 Register Reg = RISCV::X0 + RegNo;
82 Register Reg = RISCV::F0_F + RegNo;
93 Register Reg = RISCV::F8_F + RegNo;
104 Register Reg = RISCV::F0_D + RegNo;
115 Register Reg = RISCV::F8_D + RegNo;
146 Register Reg = RISCV::X8 + RegNo;
154 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV
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/freebsd-11-stable/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp1 //===- RISCV.cpp ----------------------------------------------------------===//
24 class RISCV final : public TargetInfo {
26 RISCV();
74 RISCV::RISCV() { function in class:lld::elf::RISCV
110 uint32_t RISCV::calcEFlags() const {
135 void RISCV::writeGotHeader(uint8_t *buf) const {
142 void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
149 void RISCV::writePltHeader(uint8_t *buf) const {
170 void RISCV
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DRISCVToolchain.h1 //===--- RISCVToolchain.h - RISCV ToolChain Implementations -----*- C++ -*-===//
48 namespace RISCV { namespace in namespace:clang::driver::tools
51 Linker(const ToolChain &TC) : GnuTool("RISCV::Linker", "ld", TC) {}
59 } // end namespace RISCV

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