Searched refs:READ4 (Results 1 - 25 of 47) sorted by relevance

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/freebsd-11-stable/sys/arm/freescale/imx/
H A Dimx_gpt.c54 #define READ4(_sc, _r) \ macro
57 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
59 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
225 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR)
247 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR));
266 t1 = READ4(sc, IMX_GPT_CNT);
268 t2 = READ4(sc, IMX_GPT_CNT);
305 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period);
320 WRITE4(sc, IMX_GPT_OCR3, READ4(s
[all...]
H A Dimx_gpio.c69 #define READ4(_sc, _r) \ macro
72 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
74 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
371 wrk = READ4(sc, reg);
461 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG);
540 pad = READ4(sc, IMX_GPIO_PSR_REG);
542 pad = READ4(sc, IMX_GPIO_DR_REG);
681 *val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1;
683 *val = (READ4(s
[all...]
H A Dimx6_sdma.c66 #define READ4(_sc, _reg) \ macro
92 pending = READ4(sc, SDMAARM_INTR);
214 reg = READ4(sc, SDMAARM_EVTOVR);
222 reg = READ4(sc, SDMAARM_HOSTOVR);
230 reg = READ4(sc, SDMAARM_DSPOVR);
333 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
443 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
/freebsd-11-stable/sys/arm/samsung/exynos/
H A Dexynos5_spi.c132 reg = READ4(sc, CH_CFG);
153 reg = READ4(sc, CH_CFG);
160 reg = READ4(sc, CS_REG);
169 while (READ4(sc, SPI_STATUS) & \
176 while ((READ4(sc, SPI_STATUS) & \
184 reg = READ4(sc, CS_REG);
H A Dexynos5_xhci.c159 rev = READ4(esc, GSNPSID);
172 reg = READ4(esc, GUSB3PIPECTL(0));
176 reg = READ4(esc, GUSB2PHYCFG(0));
180 reg = READ4(esc, GCTL);
184 hwparams1 = READ4(esc, GHWPARAMS1);
186 reg = READ4(esc, GCTL);
199 reg = READ4(esc, GCTL);
H A Dexynos5_common.h29 #define READ4(_sc, _reg) \ macro
H A Dexynos5_usb_phy.c182 reg = READ4(sc, USB_DRD_PHYPARAM0);
194 reg = READ4(sc, USB_DRD_PHYPARAM1);
199 reg = READ4(sc, USB_DRD_PHYUTMICLKSEL);
203 reg = READ4(sc, USB_DRD_PHYTEST);
/freebsd-11-stable/sys/arm/altera/socfpga/
H A Dsocfpga_manager.c168 reg = READ4(sc, FPGAMGR_STAT);
206 msel = READ4(sc, FPGAMGR_STAT);
222 reg = READ4(sc, FPGAMGR_CTRL);
231 reg = READ4(sc, FPGAMGR_CTRL);
236 reg = READ4(sc, FPGAMGR_CTRL);
247 reg = READ4(sc, FPGAMGR_CTRL);
260 reg = READ4(sc, FPGAMGR_CTRL);
273 if (READ4(sc, FPGAMGR_DCLKSTAT) != 0)
282 if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) {
305 reg = READ4(s
[all...]
H A Dsocfpga_common.h33 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) macro
H A Dsocfpga_gpio.c69 #define READ4(_sc, _reg) \ macro
178 version = READ4(sc, GPIO_VER_ID_CODE);
187 cfg2 = READ4(sc, GPIO_CONFIG_REG2);
196 (READ4(sc, GPIO_SWPORTA_DDR) & (1 << i)) ?
315 *val = (READ4(sc, GPIO_EXT_PORTA) & (1 << i)) ? 1 : 0;
338 reg = READ4(sc, GPIO_SWPORTA_DR);
362 reg = READ4(sc, GPIO_SWPORTA_DDR);
417 reg = READ4(sc, GPIO_SWPORTA_DR);
/freebsd-11-stable/sys/arm/freescale/vybrid/
H A Dvf_anadig.c136 reg = READ4(sc, pll_ctrl);
145 while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED))
148 reg = READ4(sc, pll_ctrl);
167 reg = READ4(sc, ANADIG_PLL4_CTRL);
208 reg = READ4(sc, ANADIG_REG_3P0);
213 reg = READ4(sc, USB_MISC(0));
217 reg = READ4(sc, USB_MISC(1));
223 READ4(sc, USB_ANALOG_USB_MISC(0)));
225 READ4(sc, USB_ANALOG_USB_MISC(1)));
H A Dvf_spi.c164 reg = READ4(sc, SPI_MCR);
172 reg = READ4(sc, SPI_RSER);
176 reg = READ4(sc, SPI_MCR);
180 reg = READ4(sc, SPI_CTAR0);
198 reg = READ4(sc, SPI_CTAR0);
232 while((READ4(sc, SPI_SR) & SR_EOQF) == 0)
235 reg = READ4(sc, SPI_SR);
241 while((READ4(sc, SPI_SR) & SR_RFDF) == 0)
H A Dvf_adc.c162 return (READ4(sc, ADC_R0));
175 reg = READ4(sc, ADC_HC0);
212 reg = READ4(sc, ADC_CFG);
218 reg = READ4(sc, ADC_GC);
223 reg = READ4(sc, ADC_HC0);
H A Dvf_common.h29 #define READ4(_sc, _reg) \ macro
H A Dvf_nfc.c203 reg = READ4(sc, NFC_CFG);
241 reg = READ4(sc, NFC_CMD2);
250 reg = READ4(sc, NFC_CMD1);
264 reg = READ4(sc, NFC_CMD2);
270 reg = READ4(sc, NFC_CMD2);
277 reg = READ4(sc, NFC_CAR);
285 reg = READ4(sc, NFC_RAR);
294 reg = READ4(sc, NFC_CMD2);
299 while (READ4(sc, NFC_CMD2) & (1 << CMD2_START_SHIFT))
413 sr1 = READ4(s
[all...]
H A Dvf_edma.c101 interrupts = READ4(sc, DMA_INT);
124 reg = READ4(sc, DMA_ERR);
128 reg, READ4(sc, DMA_ES));
197 reg = READ4(sc, DMA_ERQ);
244 reg = READ4(sc, DMA_ERQ);
249 reg = READ4(sc, DMA_EEI);
H A Dvf_sai.c357 reg = READ4(sc, I2S_TCR2);
611 READ4(sc, I2S_TCSR));
623 reg = READ4(sc, I2S_TCSR);
627 reg = READ4(sc, I2S_TCR3);
634 reg = READ4(sc, I2S_TCR2);
642 reg = READ4(sc, I2S_TCR3);
647 reg = READ4(sc, I2S_TCR4);
655 reg = READ4(sc, I2S_TCR5);
665 reg = READ4(sc, I2S_TCSR);
H A Dvf_ccm.c378 reg = READ4(sc, clk->sel_reg);
384 reg = READ4(sc, clk->reg);
461 reg = READ4(sc, CCM_CCR);
467 if (READ4(sc, CCM_CSR) & FXOSC_RDY) {
/freebsd-11-stable/sys/dev/dwc/
H A Dif_dwc.c82 #define READ4(_sc, _reg) \ macro
311 reg = READ4(sc, OPERATION_MODE);
316 reg = READ4(sc, OPERATION_MODE);
321 reg = READ4(sc, MAC_CONFIGURATION);
326 reg = READ4(sc, OPERATION_MODE);
335 reg = READ4(sc, MMC_CONTROL);
352 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
353 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
355 READ4(sc, RXOVERSIZE_G) + READ4(s
[all...]
/freebsd-11-stable/sys/dev/mmc/host/
H A Ddwmmc.c66 #define READ4(_sc, _reg) \ macro
182 reg = READ4(sc, SDMMC_CTRL);
188 if (!(READ4(sc, SDMMC_CTRL) & reset_bits))
291 cmd->resp[3] = READ4(sc, SDMMC_RESP0);
292 cmd->resp[2] = READ4(sc, SDMMC_RESP1);
293 cmd->resp[1] = READ4(sc, SDMMC_RESP2);
294 cmd->resp[0] = READ4(sc, SDMMC_RESP3);
299 cmd->resp[0] = READ4(sc, SDMMC_RESP0);
344 reg = READ4(sc, SDMMC_MINTSTS);
397 reg = READ4(s
[all...]
/freebsd-11-stable/sys/dev/xilinx/
H A Daxi_quad_spi.c67 #define READ4(_sc, _reg) \ macro
168 while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY))
171 data = READ4(sc, SPI_DRR);
199 reg = READ4(sc, SPI_SSR);
210 reg = READ4(sc, SPI_SSR);
/freebsd-11-stable/sys/dev/beri/virtio/
H A Dvirtio.h35 #define READ4(_sc, _reg) \ macro
/freebsd-11-stable/sys/dev/altera/pio/
H A Dpio.c60 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) macro
117 return (READ4(sc, PIO_DATA));
/freebsd-11-stable/sys/dev/hatm/
H A Dif_hatmvar.h472 #define READ4(SC,OFF) bus_space_read_4(SC->memt, SC->memh, (OFF)) macro
487 #define READ_SUNI(SC,OFF) READ4(SC, HE_REGO_SUNI + 4 * (OFF))
495 while((READ4(SC, HE_REGO_LB_MEM_ACCESS) & HE_REGM_LB_MEM_HNDSHK))\
497 READ4(SC, HE_REGO_LB_MEM_DATA); \
505 while((READ4(SC, HE_REGO_LB_MEM_ACCESS) & HE_REGM_LB_MEM_HNDSHK))\
514 while((READ4(SC, HE_REGO_CON_CTL) & HE_REGM_CON_STATUS) != 0) \
522 while((READ4(SC, HE_REGO_CON_CTL) & HE_REGM_CON_STATUS) != 0) \
524 READ4(SC, HE_REGO_CON_DAT); \
/freebsd-11-stable/sys/mips/mediatek/
H A Dmtk_intr_v1.c104 #define READ4(_sc, _reg) bus_read_4((_sc)->pic_res[0], _reg) macro
234 intr = READ4(sc, MTK_IRQ1STAT);
251 intr = READ4(sc, MTK_IRQ0STAT);

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