Searched refs:ProcModel (Results 1 - 4 of 4) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp95 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
97 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
99 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
103 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
105 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
108 const CodeGenProcModel &ProcModel);
110 const CodeGenProcModel &ProcModel);
112 const CodeGenProcModel &ProcModel);
113 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
385 for (const CodeGenProcModel &ProcModel
619 EmitProcessorResourceSubUnits( const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
642 EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
656 EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, unsigned NumRegisterFiles, unsigned NumCostEntries, raw_ostream &OS) argument
673 EmitRegisterFileTables(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
725 EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
749 EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
773 EmitProcessorResources(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
830 FindWriteResources( const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) argument
883 FindReadAdvance(const CodeGenSchedRW &SchedRead, const CodeGenProcModel &ProcModel) argument
982 GenSchedClassTables(const CodeGenProcModel &ProcModel, SchedClassTables &SchedTables) argument
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H A DDFAPacketizerEmitter.cpp219 for (const CodeGenProcModel &ProcModel : CGS.procModels()) {
220 if (ProcModel.hasItineraries()) {
221 auto NS = ProcModel.ItinsDef->getValueAsString("PacketizerNamespace");
222 ItinsByNamespace[NS].push_back(&ProcModel);
H A DCodeGenSchedule.cpp797 const CodeGenProcModel &ProcModel) const {
805 if (&getProcModel(ModelDef) != &ProcModel)
810 "defined for processor " + ProcModel.ModelName +
816 RWSeq, IsRead,ProcModel); local
827 expandRWSeqForProc(Idx, RWSeq, IsRead, ProcModel);
937 const CodeGenProcModel &ProcModel = local
939 ProcIndices.push_back(ProcModel.Index);
940 LLVM_DEBUG(dbgs() << "InstRW on " << ProcModel.ModelName << " for "
1154 for (CodeGenProcModel &ProcModel : ProcModels) {
1155 if (!ProcModel
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H A DCodeGenSchedule.h561 const CodeGenProcModel &ProcModel) const;

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