Searched refs:PredR (Results 1 - 8 of 8) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp125 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {}
131 unsigned PredR = 0; member in struct:__anon2238::FlowPattern
146 << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
197 MachineInstr *MI, unsigned PredR, bool IfTrue);
200 unsigned PredR, bool IfTrue);
203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
253 Register PredR = T1I->getOperand(0).getReg();
271 // Record the true/false blocks in such a way that "true" means "if (PredR)",
272 // and "false" means "if (!PredR)"
709 predicateInstr(MachineBasicBlock *ToB, MachineBasicBlock::iterator At, MachineInstr *MI, unsigned PredR, bool IfTrue) argument
760 predicateBlockNB(MachineBasicBlock *ToB, MachineBasicBlock::iterator At, MachineBasicBlock *FromB, unsigned PredR, bool IfTrue) argument
777 buildMux(MachineBasicBlock *B, MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) argument
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H A DHexagonGenMux.cpp92 unsigned PredR = 0; member in struct:__anon2248::HexagonGenMux::CondsetInfo
108 unsigned DefR, PredR; member in struct:__anon2248::HexagonGenMux::MuxInfo
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
256 if (F != CM.end() && F->second.PredR != PR) {
263 F->second.PredR = PR;
344 .addReg(MX.PredR)
H A DHexagonExpandCondsets.cpp221 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
743 /// under the conditions given by PredR and Cond, and this function will ignore
746 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
759 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
763 // Check the defs. If the PredR is defined, invalidate it. If RD is
769 if (RR.Reg == PredR) {
853 /// PredR and Cond) at the point indicated by Where.
909 unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
918 if (!MI->readsRegister(PredR) || (Con
745 getReachingDefForPred(RegisterRef RD, MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) argument
908 renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR, bool Cond, MachineBasicBlock::iterator First, MachineBasicBlock::iterator Last) argument
958 Register PredR = MP.getReg(); local
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H A DHexagonHardwareLoops.cpp462 unsigned PredR, PredPos, PredRegFlags; local
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
466 MachineInstr *PredI = MRI->getVRegDef(PredR);
1337 Register PredR = CmpI->getOperand(0).getReg();
1345 if (MO.getReg() == PredR) // Found an intervening use of PredR.
1915 Register PredR = PN->getOperand(i).getReg(); local
1921 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
H A DHexagonISelLowering.cpp347 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); local
348 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
354 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp308 /// and PredR are their predicates, respectively.
315 ICmpInst::Predicate &PredR) {
356 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) {
391 if (!ICmpInst::isEquality(PredR))
433 unsigned RightType = getMaskedICmpType(A, D, E, PredR);
444 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
475 if (PredR != NewCC)
574 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
577 assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
591 PredL, PredR, Builde
311 getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C, Value *&D, Value *&E, ICmpInst *LHS, ICmpInst *RHS, ICmpInst::Predicate &PredL, ICmpInst::Predicate &PredR) argument
441 foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed( ICmpInst *LHS, ICmpInst *RHS, bool IsAnd, Value *A, Value *B, Value *C, Value *D, Value *E, ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, llvm::InstCombiner::BuilderTy &Builder) argument
571 foldLogOpOfMaskedICmpsAsymmetric( ICmpInst *LHS, ICmpInst *RHS, bool IsAnd, Value *A, Value *B, Value *C, Value *D, Value *E, ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, unsigned LHSMask, unsigned RHSMask, llvm::InstCombiner::BuilderTy &Builder) argument
609 ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); local
1363 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); local
2819 ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp380 CmpInst::Predicate PredL, PredR; local
383 match(CondR, m_Cmp(PredR, m_Specific(X), m_Specific(Y))) &&
384 CmpInst::getInversePredicate(PredL) == PredR)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp1804 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate();
1805 if ((PredL == FCmpInst::FCMP_ORD && PredR == FCmpInst::FCMP_ORD && IsAnd) ||
1806 (PredL == FCmpInst::FCMP_UNO && PredR == FCmpInst::FCMP_UNO && !IsAnd)) {

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