Searched refs:P0 (Results 1 - 25 of 28) sorted by relevance

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/freebsd-11-stable/lib/msun/src/
H A Ds_cbrt.c30 P0 = 1.87595182427177009643, /* 0x3ffe03e6, 0x0f61e692 */ variable
89 t=t*((P0+r*(P1+r*P2))+((r*r)*r)*(P3+r*P4));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp99 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
109 // P0 = cmp.eq(Rs,#u2)
112 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
143 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
157 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
178 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
186 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt;
188 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t;
190 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt;
192 return (PredReg == Hexagon::P0)
[all...]
H A DHexagonMCChecker.h101 return (Hexagon::P0 == R || Hexagon::P1 == R || Hexagon::P2 == R ||
H A DHexagonMCDuplexInfo.cpp299 if ((HexagonMCInstrInfo::isPredReg(SrcReg) && (Hexagon::P0 == SrcReg)) &&
312 if (Hexagon::P0 == SrcReg) {
404 // if ([!]P0[.new]) Rd = #0
407 // P0 = cmp.eq(Rs,#u2)
475 // if ([!]P0[.new]) Rd = #0
479 PredReg = MCI.getOperand(1).getReg(); // P0
481 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {
486 // P0 = cmp.eq(Rs,#u2)
489 if (Hexagon::P0 == DstReg &&
694 case Hexagon::P0
[all...]
H A DHexagonMCInstrInfo.cpp659 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_ldlib_asm.S63 #define ce P0
162 #define ce P0
H A Dfastmath2_dlib_asm.S73 #define ce P0
174 #define ce P0
H A Dfastmath_dlib_asm.S81 #define ce P0
216 #define ce P0
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp108 Value *P0 = Phi.getOperand(0), *P1 = Phi.getOperand(1); local
110 Intrinsic::ID IID = matchRotate(P0, RotSrc, RotAmt);
113 if (IID == Intrinsic::not_intrinsic || RotSrc != P0)
/freebsd-11-stable/lib/msun/bsdsrc/
H A Db_tgamma.c97 #define P0 6.21389571821820863029017800727e-01 macro
255 p = P0 + z*(P1 + z*(P2 + z*(P3 + z*P4)));
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerInfo.h191 /// True iff P0 and P1 are true.
193 Predicate all(Predicate P0, Predicate P1) { argument
195 return P0(Query) && P1(Query);
200 Predicate all(Predicate P0, Predicate P1, Args... args) { argument
201 return all(all(P0, P1), args...);
/freebsd-11-stable/secure/lib/libcrypto/arm/
H A Dghash-armv4.S396 veor d16, d16, d17 @ t0 = (L) (P0 + P1) << 8
434 veor d16, d16, d17 @ t0 = (L) (P0 + P1) << 8
471 veor d16, d16, d17 @ t0 = (L) (P0 + P1) << 8
H A Darmv4-gf2m.S167 veor d2, d2, d3 @ t0 = (L) (P0 + P1) << 8
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp66 P0, P1, P2, P3, 0
H A DHexagonInstrInfo.cpp3312 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3319 // P0 = cmp.eq(Rs,#u2)
3323 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3348 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3363 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3390 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3398 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3402 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3832 (Hexagon::P0 == SrcReg)) &&
3844 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0
[all...]
H A DHexagonConstExtenders.cpp1358 auto P0 = MaxAlign(Tree.nodesWith(R.Min, false), R.Align, R.Offset); local
1360 if (R.Align < P0.first)
1361 CandSet.insert(adjustUp(R.Min, P0.first, P0.second));
H A DHexagonLoopIdiomRecognition.cpp1530 Value *P = PV.P, *Q = PV.Q, *P0 = P; local
1534 P0 = P = B.CreateXor(P, PV.M);
1560 R = B.CreateXor(R, B.CreateIntCast(P0, R->getType(), false));
/freebsd-11-stable/cddl/usr.sbin/dwatch/
H A Ddwatch976 $( pproc -P0 )
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp2773 CmpInst::Predicate P0 = cast<CmpInst>(VL0)->getPredicate();
2774 CmpInst::Predicate SwapP0 = CmpInst::getSwappedPredicate(P0);
2778 if ((Cmp->getPredicate() != P0 && Cmp->getPredicate() != SwapP0) ||
2797 assert(P0 == SwapP0 && "Commutative Predicate mismatch");
2805 if (Cmp->getPredicate() != P0)
4224 CmpInst::Predicate P0 = cast<CmpInst>(VL0)->getPredicate();
4227 V = Builder.CreateFCmp(P0, L, R);
4229 V = Builder.CreateICmp(P0, L, R);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp629 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp1616 ICmpInst::Predicate P0 = Cmp0->getPredicate(), P1 = Cmp1->getPredicate(); local
1618 !match(Cmp1->getOperand(1), m_Zero()) || P0 != P1)
1621 if ((IsAnd && P0 != ICmpInst::ICMP_NE) || (!IsAnd && P1 != ICmpInst::ICMP_EQ))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp602 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp873 case Hexagon::P0:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp1230 return ARM::P0;
1467 return ARM::P0;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp856 MI.insert(VCCI, MCOperand::createReg(ARM::P0));
6289 return ARM::P0;

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