| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | PredicateExpander.h | 58 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, int ImmVal,
60 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, StringRef ImmVal,
62 void expandCheckImmOperandSimple(raw_ostream &OS, int OpIndex,
64 void expandCheckRegOperand(raw_ostream &OS, int OpIndex, const Record *Reg,
66 void expandCheckRegOperandSimple(raw_ostream &OS, int OpIndex,
77 void expandCheckIsRegOperand(raw_ostream &OS, int OpIndex);
78 void expandCheckIsImmOperand(raw_ostream &OS, int OpIndex);
79 void expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex);
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| H A D | PredicateExpander.cpp | 21 void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex, argument
26 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
33 void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex, argument
37 expandCheckImmOperandSimple(OS, OpIndex, FunctionMapper);
41 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
49 int OpIndex,
55 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
61 void PredicateExpander::expandCheckRegOperand(raw_ostream &OS, int OpIndex, argument
68 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
81 int OpIndex,
48 expandCheckImmOperandSimple(raw_ostream &OS, int OpIndex, StringRef FunctionMapper) argument
80 expandCheckRegOperandSimple(raw_ostream &OS, int OpIndex, StringRef FunctionMapper) argument
93 expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex) argument
191 expandCheckIsRegOperand(raw_ostream &OS, int OpIndex) argument
196 expandCheckIsImmOperand(raw_ostream &OS, int OpIndex) argument
[all...] |
| H A D | AsmWriterEmitter.cpp | 693 int OpIndex, PrintIndex; local
694 std::tie(OpIndex, PrintIndex) = getOpData(Name);
697 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
702 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 315 Write.OpIndex = i;
330 dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
342 Write.OpIndex = ~CurrentDef;
360 dbgs() << "\t\t[Def][I] OpIdx=" << ~Write.OpIndex
369 Write.OpIndex = MCDesc.getNumOperands() - 1;
375 dbgs() << "\t\t[Def][O] OpIdx=" << Write.OpIndex
394 for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
395 I < NumVariadicOps && !AssumeUsesOnly; ++I, ++OpIndex) {
396 const MCOperand &Op = MCI.getOperand(OpIndex);
401 Write.OpIndex
[all...] |
| H A D | Instruction.cpp | 125 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID "
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsELFStreamer.cpp | 43 for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) {
44 const MCOperand &Op = Inst.getOperand(OpIndex);
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 40 // a bitwise not of the OpIndex.
41 int OpIndex; member in struct:llvm::mca::WriteDescriptor
61 bool isImplicitWrite() const { return OpIndex < 0; };
68 // implicit read is the bitwise not of field OpIndex.
69 int OpIndex; member in struct:llvm::mca::ReadDescriptor
79 bool isImplicitRead() const { return OpIndex < 0; };
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TypeBasedAliasAnalysis.cpp | 297 unsigned OpIndex = FirstFieldOpNo + FieldIndex * NumOpsPerField; local
298 auto *TypeNode = cast<MDNode>(getNode()->getOperand(OpIndex));
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| H A D | ScalarEvolution.cpp | 6053 for (unsigned OpIndex = 0; OpIndex < I->getNumOperands(); ++OpIndex) {
6056 if (!isSCEVable(I->getOperand(OpIndex)->getType()))
6058 const SCEV *Op = getSCEV(I->getOperand(OpIndex));
6063 if (OtherOpIndex != OpIndex) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 1613 unsigned OpIndex; local
1618 OpIndex = 0;
1621 OpIndex = 1;
1624 OpIndex = 2;
1627 OpIndex = 3;
1632 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
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| H A D | X86FastISel.cpp | 1914 unsigned TypeIndex, OpIndex; local
1928 case Instruction::SDiv: OpIndex = 0; break;
1929 case Instruction::SRem: OpIndex = 1; break;
1930 case Instruction::UDiv: OpIndex = 2; break;
1931 case Instruction::URem: OpIndex = 3; break;
1935 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
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| H A D | X86ISelLowering.cpp | 16593 unsigned OpIndex = i / 2;
16594 if (Ops[OpIndex].isUndef())
16595 Ops[OpIndex] = Op;
16596 else if (Ops[OpIndex] != Op)
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 458 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); local
459 MCOperand &MCO = MI.getOperand(OpIndex);
|