/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 186 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 188 BinaryOperator *BO = BinaryOperator::CreateNeg(Op0, I.getName()); 241 if (Op0->hasOneUse()) { 244 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) 246 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) 268 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { 280 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Constant(Op1C))) 284 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Neg(m_Value(Y)))) { 287 cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap() && 302 BinaryOperator *Div = dyn_cast<BinaryOperator>(Op0); 681 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 846 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 859 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 885 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument 1314 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineAddSub.cpp | 828 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); local 839 match(Op0, m_OneUse(m_ZExt(m_NUWAdd(m_Value(X), m_APInt(C2))))) && 849 if (match(Op0, m_OneUse(m_SExt(m_NSWAdd(m_Value(X), m_Constant(NarrowC)))))) { 856 if (match(Op0, m_OneUse(m_ZExt(m_NUWAdd(m_Value(X), m_Constant(NarrowC)))))) { 867 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); local 879 if (match(Op0, m_Sub(m_Constant(Op00C), m_Value(X)))) 885 if (match(Op0, m_OneUse(m_Sub(m_Value(X), m_Value(Y)))) && 890 if (match(Op0, m_ZExt(m_Value(X))) && 894 if (match(Op0, m_SExt(m_Value(X))) && 899 if (match(Op0, m_No [all...] |
H A D | InstCombineAndOrXor.cpp | 1163 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 1166 return getNewICmpValue(Code, IsSigned, Op0, Op1, Builder); 1421 Value *Op0 = BO.getOperand(0), *Op1 = BO.getOperand(1), *X; local 1424 std::swap(Op0, Op1); 1430 if (!match(Op0, m_FCmp(Pred, m_Value(X), m_AnyZeroFP())) || Pred != NanPred || 1449 NewFCmpInst->copyIRFlags(Op0); 1539 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1540 CastInst *Cast0 = dyn_cast<CastInst>(Op0); 1604 Value *Op0 = I.getOperand(0); local 1608 // Operand complexity canonicalization guarantees that the 'or' is Op0 1630 Value *Op0 = I.getOperand(0); local 1687 Value *Op0 = And.getOperand(0), *Op1 = And.getOperand(1); local 1981 Value *Op0 = Or.getOperand(0), *Op1 = Or.getOperand(1); local 2263 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 2495 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2740 Value *Op0 = I.getOperand(0); local 2809 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local [all...] |
H A D | InstCombineShifts.cpp | 364 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 365 assert(Op0->getType() == Op1->getType()); 371 return BinaryOperator::Create(I.getOpcode(), Op0, NewExt); 379 if (isa<Constant>(Op0)) 385 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) 396 if (match(Op0, m_Constant()) && match(Op1, m_Add(m_Value(A), m_Constant(C)))) 400 I.getOpcode(), Builder.CreateBinOp(I.getOpcode(), Op0, C), A); 682 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, argument 693 canEvaluateShifted(Op0, Op1C->getZExtValue(), isLeftShift, *this, &I)) { 697 << *Op0 << "\ [all...] |
H A D | InstCombineCompares.cpp | 1446 Value *Op0 = Cmp.getOperand(0), *Op1 = Cmp.getOperand(1); local 1450 match(Op0, m_Add(m_Add(m_Value(A), m_Value(B)), m_ConstantInt(CI2)))) 3169 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 3171 Instruction *LHSI = dyn_cast<Instruction>(Op0); 3704 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 3707 BinaryOperator *BO0 = dyn_cast<BinaryOperator>(Op0); 3717 if (match(Op0, m_OneUse(m_c_Add(m_Specific(Op1), m_Value(X)))) && 3720 // Op0 u>/u<= (Op0 + X) --> X u>/u<= ~Op0 4072 Value *Op0 = Cmp.getOperand(0); local 4829 swapMayExposeCSEOpportunities(const Value *Op0, const Value *Op1) argument 4961 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 5428 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 5457 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 6045 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 244 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) 245 if (Op0->getOpcode() == OpcodeToExpand) { 247 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; 304 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); 308 if (Op0 && Op0->getOpcode() == Opcode) { 309 Value *A = Op0->getOperand(0); 310 Value *B = Op0->getOperand(1); 350 if (Op0 601 foldOrCommuteConstant(Instruction::BinaryOps Opcode, Value *&Op0, Value *&Op1, const SimplifyQuery &Q) argument 617 SimplifyAddInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, const SimplifyQuery &Q, unsigned MaxRecurse) argument 681 SimplifyAddInst(Value *Op0, Value *Op1, bool IsNSW, bool IsNUW, const SimplifyQuery &Query) argument 737 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const SimplifyQuery &Q, unsigned MaxRecurse) argument 865 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const SimplifyQuery &Q) argument 872 SimplifyMulInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 926 SimplifyMulInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 932 simplifyDivRem(Value *Op0, Value *Op1, bool IsDiv) argument 1049 simplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1107 simplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1151 SimplifySDivInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1160 SimplifySDivInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 1166 SimplifyUDivInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1171 SimplifyUDivInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 1177 SimplifySRemInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1192 SimplifySRemInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 1198 SimplifyURemInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1203 SimplifyURemInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 1236 SimplifyShift(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1286 SimplifyRightShift(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, bool isExact, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1313 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1338 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const SimplifyQuery &Q) argument 1345 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1376 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const SimplifyQuery &Q) argument 1383 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const SimplifyQuery &Q, unsigned MaxRecurse) argument 1407 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const SimplifyQuery &Q) argument 1525 simplifyAndOfICmpsWithSameOperands(ICmpInst *Op0, ICmpInst *Op1) argument 1550 simplifyOrOfICmpsWithSameOperands(ICmpInst *Op0, ICmpInst *Op1) argument 1651 simplifyAndOfICmpsWithAdd(ICmpInst *Op0, ICmpInst *Op1, const InstrInfoQuery &IIQ) argument 1698 simplifyAndOfICmps(ICmpInst *Op0, ICmpInst *Op1, const SimplifyQuery &Q) argument 1724 simplifyOrOfICmpsWithAdd(ICmpInst *Op0, ICmpInst *Op1, const InstrInfoQuery &IIQ) argument 1771 simplifyOrOfICmps(ICmpInst *Op0, ICmpInst *Op1, const SimplifyQuery &Q) argument 1835 simplifyAndOrOfCmps(const SimplifyQuery &Q, Value *Op0, Value *Op1, bool IsAnd) argument 1901 omitCheckForZeroBeforeMulWithOverflow(Value *Op0, Value *Op1) argument 1924 omitCheckForZeroBeforeInvertedMulWithOverflow(Value *Op0, Value *NotOp1) argument 1944 SimplifyAndInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 2094 SimplifyAndInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 2100 SimplifyOrInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 2238 SimplifyOrInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 2244 SimplifyXorInst(Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument 2283 SimplifyXorInst(Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 4371 foldIdentityShuffles(int DestElt, Value *Op0, Value *Op1, int MaskVal, Value *RootVec, unsigned MaxRecurse) argument 4419 SimplifyShuffleVectorInst(Value *Op0, Value *Op1, Constant *Mask, Type *RetTy, const SimplifyQuery &Q, unsigned MaxRecurse) argument 4520 SimplifyShuffleVectorInst(Value *Op0, Value *Op1, Constant *Mask, Type *RetTy, const SimplifyQuery &Q) argument 4578 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q, unsigned MaxRecurse) argument 4625 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q, unsigned MaxRecurse) argument 4670 SimplifyFMAFMul(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q, unsigned MaxRecurse) argument 4704 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q, unsigned MaxRecurse) argument 4713 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q) argument 4719 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q) argument 4724 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q) argument 4729 SimplifyFMAFMul(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q) argument 4734 SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q, unsigned) argument 4774 SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q) argument 4779 SimplifyFRemInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q, unsigned) argument 4802 SimplifyFRemInst(Value *Op0, Value *Op1, FastMathFlags FMF, const SimplifyQuery &Q) argument 5006 simplifyUnaryIntrinsic(Function *F, Value *Op0, const SimplifyQuery &Q) argument 5079 simplifyBinaryIntrinsic(Function *F, Value *Op0, Value *Op1, const SimplifyQuery &Q) argument 5256 Value *Op0 = Call->getArgOperand(0), *Op1 = Call->getArgOperand(1), local 5278 Value *Op0 = Call->getArgOperand(0); local 5323 SimplifyFreezeInst(Value *Op0) argument 5331 SimplifyFreezeInst(Value *Op0, const SimplifyQuery &Q) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 137 Ops[1].getAsInteger(10, Op0); 142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 149 uint32_t Op0 = (Bits >> 14) & 0x3; 155 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZTDC.cpp | 123 Value *Op0 = I.getOperand(0); local 130 auto &Sem = Op0->getType()->getFltSemantics(); 216 if (CallInst *CI = dyn_cast<CallInst>(Op0)) { 222 Op0 = CI->getArgOperand(0); 229 converted(&I, Op0, Mask, Worthy); 233 Value *Op0 = I.getOperand(0); local 239 if (auto *Cast = dyn_cast<BitCastInst>(Op0)) { 259 } else if (auto *CI = dyn_cast<CallInst>(Op0)) { 288 Value *Op0, *Op1; local 291 std::tie(Op0, Mask [all...] |
H A D | SystemZISelLowering.cpp | 37 : Op0(Op0In), Op1(Op1In), Chain(ChainIn), 41 SDValue Op0, Op1; member in struct:__anon2410::Comparison 46 // The opcode that should be used to compare Op0 and Op1. 2016 if (!C.Op0.hasOneUse() || 2017 C.Op0.getOpcode() != ISD::LOAD || 2022 auto *Load = cast<LoadSDNode>(C.Op0); 2033 // Make sure that ConstOp1 is in range of C.Op0. 2067 if (C.Op0.getValueType() != MVT::i32 || 2069 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(), 2074 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), C.Op0 3505 SDValue Op0 = Op.getOperand(0); local 4397 getPermuteNode(SelectionDAG &DAG, const SDLoc &DL, const Permute &P, SDValue Op0, SDValue Op1) argument 4648 buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op0, SDValue Op1) argument 4664 joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0, SDValue Op1) argument 4925 SDValue Op0 = Op.getOperand(0); local 5668 SDValue Op0 = N->getOperand(0); local 5896 SDValue Op0 = N->getOperand(0); local 5941 SDValue Op0 = N->getOperand(OpNo); local 6007 SDValue Op0 = N->getOperand(OpNo); local 6142 SDValue Op0 = Op.getOperand(0); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 108 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 110 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 121 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 123 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 146 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 148 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 488 Scatterer Op0 = scatter(&I, I.getOperand(0)); local 490 assert(Op0.size() == NumElems && "Mismatched binary operation"); 495 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 587 Scatterer Op0 local 593 Value *Op0 = SI.getOperand(0); local 629 Value *Op0 = GEPI.getOperand(0); local 671 Scatterer Op0 = scatter(&CI, CI.getOperand(0)); local 691 Scatterer Op0 = scatter(&BCI, BCI.getOperand(0)); local 743 Scatterer Op0 = scatter(&SVI, SVI.getOperand(0)); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 358 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 363 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 369 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 377 unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, 398 const TargetRegisterClass *RC, unsigned Op0, 404 const TargetRegisterClass *RC, unsigned Op0, 410 const TargetRegisterClass *RC, unsigned Op0, 417 const TargetRegisterClass *RC, unsigned Op0, 423 const TargetRegisterClass *RC, unsigned Op0, 435 const TargetRegisterClass *RC, unsigned Op0, [all...] |
H A D | SelectionDAGAddressAnalysis.h | 78 // Returns true `Op0` and `Op1` can be proven to alias/not alias, in 80 static bool computeAliasing(const SDNode *Op0,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 639 unsigned Op0 = getRegForValue(I->getOperand(0)); local 640 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. 662 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 679 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); 1559 unsigned Op0 = getRegForValue(I->getOperand(0)); local 1560 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. 1573 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0); 1579 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1782 const Value *Op0 = EVI->getOperand(0); local 1783 Type *AggTy = Op0 1991 fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 2064 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 2085 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 2109 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 2137 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 2159 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 2203 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 2245 fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 2259 fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument [all...] |
H A D | TargetLowering.cpp | 723 SDValue Op0 = Op.getOperand(0); local 730 Op0.getScalarValueSizeInBits() == DemandedBits.getBitWidth() && 731 getBooleanContents(Op0.getValueType()) == 739 return Op0; 1020 SDValue Op0 = Op.getOperand(0); local 1026 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO, 1042 Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1); 1046 Op0 = DemandedOp0 ? DemandedOp0 : Op0; 1048 SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op 1055 SDValue Op0 = Op.getOperand(0); local 1133 SDValue Op0 = Op.getOperand(0); local 1179 SDValue Op0 = Op.getOperand(0); local 1293 SDValue Op0 = Op.getOperand(0); local 1321 SDValue Op0 = Op.getOperand(0); local 1418 SDValue Op0 = Op.getOperand(0); local 1477 SDValue Op0 = Op.getOperand(0); local 1541 SDValue Op0 = Op.getOperand(0); local 1599 SDValue Op0 = Op.getOperand(0); local 1989 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1); local 3493 SDValue Op0 = N0; local 4638 SDValue Op0 = N->getOperand(0); local 5154 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); local 5396 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
H A D | AggressiveInstCombine.cpp | 177 Value *Op0, *Op1; local 182 if (match(V, m_And(m_Value(Op0), m_One()))) { 184 return matchAndOrChain(Op0, MOps); 186 if (match(V, m_And(m_Value(Op0), m_Value(Op1)))) 187 return matchAndOrChain(Op0, MOps) && matchAndOrChain(Op1, MOps); 190 if (match(V, m_Or(m_Value(Op0), m_Value(Op1)))) 191 return matchAndOrChain(Op0, MOps) && matchAndOrChain(Op1, MOps); 284 Value *Op0 = I.getOperand(0); local 288 if ((match(Op0, m_Mul(m_Value(MulOp0), m_SpecificInt(Mask01)))) &&
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 95 const MachineOperand &Op0 = MI->getOperand(Operand); local 96 if (Op0.isReg()) { 98 AM.Base.Reg = Op0.getReg(); 101 AM.Base.FrameIndex = Op0.getIndex();
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H A D | X86FloatingPoint.cpp | 1296 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); local 1298 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0); 1306 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1311 moveToTop(Op0, I); // Move dead operand to TOS. 1312 TOS = Op0; 1322 duplicateToTop(Op0, Dest, I); 1323 Op0 = TOS = Dest; 1330 duplicateToTop(Op0, Dest, I); 1331 Op0 = TOS = Dest; 1337 assert((TOS == Op0 || TO 1391 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); local 1417 unsigned Op0 = getFPReg(MI.getOperand(0)); local [all...] |
H A D | X86RegisterBankInfo.cpp | 213 auto &Op0 = MI.getOperand(0); local 215 const LLT Ty0 = MRI.getType(Op0.getReg()); 242 auto &Op0 = MI.getOperand(0); local 244 const LLT Ty0 = MRI.getType(Op0.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 202 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0, argument 205 assert((Res == Op0 && Res == Op1) && "type mismatch"); 208 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0, argument 211 assert((Res == Op0) && "type mismatch"); 215 const SrcOp &Op0, 218 Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch"); 221 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}); 225 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0, argument 231 Res = Op0; 235 Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0)); 214 buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) argument 240 buildPtrMask(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits) argument 393 buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1) argument 400 buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn) argument 698 buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) argument 705 buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional<unsigned> Flags) argument 714 buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional<unsigned> Flags) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | GetElementPtrTypeIterator.h | 151 gep_type_begin(Type *Op0, ArrayRef<T> A) { argument 152 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin()); 157 gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelDAGToDAG.cpp | 253 SDValue Op0, Op1, AluOp; local 258 if (!selectAddrRr(Op, Op0, Op1, AluOp) && 259 !selectAddrRi(Op, Op0, Op1, AluOp)) 264 OutOps.push_back(Op0);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | InstructionSimplify.h | 176 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, 180 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, 184 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, 233 Value *SimplifyShuffleVectorInst(Value *Op0, Value *Op1, Constant *Mask,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | ProfileSummary.cpp | 126 ConstantAsMetadata *Op0 = 133 if (!Op0 || !Op1 || !Op2) 135 Summary.emplace_back(cast<ConstantInt>(Op0->getValue())->getZExtValue(),
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H A D | AutoUpgrade.cpp | 979 Value *Op0, Value *Op1) { 983 return Op0; 985 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 986 return Builder.CreateSelect(Mask, Op0, Op1); 990 Value *Op0, Value *Op1) { 994 return Op0; 1001 return Builder.CreateSelect(Mask, Op0, Op1); 1007 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, argument 1013 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1025 return llvm::Constant::getNullValue(Op0 978 EmitX86Select(IRBuilder< &Builder, Value *Mask, Value *Op0, Value *Op1) argument 989 EmitX86ScalarSelect(IRBuilder< &Builder, Value *Mask, Value *Op0, Value *Op1) argument 1117 Value *Op0 = CI.getOperand(0); local 1203 Value *Op0 = CI.getArgOperand(0); local 1275 Value *Op0 = CI.getArgOperand(0); local 1290 Value *Op0 = CI.getArgOperand(0); local 1355 Value *Op0 = CI.getArgOperand(0); local 1847 Value *Op0 = CI->getArgOperand(0); local 2428 Value *Op0 = CI->getArgOperand(0); local 2442 Value *Op0 = CI->getArgOperand(0); local 2487 Value *Op0 = CI->getArgOperand(0); local 2511 Value *Op0 = CI->getArgOperand(0); local 2565 Value *Op0 = CI->getArgOperand(0); local 2587 Value *Op0 = CI->getArgOperand(0); local 2606 Value *Op0 = CI->getArgOperand(0); local 2624 Value *Op0 = CI->getArgOperand(0); local 2651 Value *Op0 = CI->getArgOperand(0); local 2672 Value *Op0 = CI->getArgOperand(0); local 2688 Value *Op0 = CI->getArgOperand(0); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 139 SDValue Op0 = Node->getOperand(0); local 147 isConstantMask(Op0.getNode(), Mask)) { 153 CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0.getOperand(0),
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