Searched refs:NodeOrder (Results 1 - 10 of 10) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp55 if (TryCand.Reason != NodeOrder && TryCand.Reason != NoCand)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp1444 /// as the predecessors of the elements of NodeOrder that are not also in
1445 /// NodeOrder.
1446 static bool pred_L(SetVector<SUnit *> &NodeOrder, argument
1450 for (SetVector<SUnit *>::iterator I = NodeOrder.begin(), E = NodeOrder.end();
1458 if (NodeOrder.count(PI->getSUnit()) == 0)
1469 if (NodeOrder.count(IS->getSUnit()) == 0)
1477 /// as the successors of the elements of NodeOrder that are not also in
1478 /// NodeOrder.
1479 static bool succ_L(SetVector<SUnit *> &NodeOrder, argument
[all...]
H A DMachineScheduler.cpp2589 case NodeOrder: return "ORDER ";
3002 TryCand.Reason = NodeOrder;
3095 TryCand.Reason = NodeOrder;
3367 TryCand.Reason = NodeOrder;
3398 TryCand.Reason = NodeOrder;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h127 NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure, enumerator in enum:llvm::ConvergingVLIWScheduler::CandResult
H A DHexagonMachineScheduler.cpp791 FoundCandidate = NodeOrder;
804 FoundCandidate = NodeOrder;
865 FoundCandidate = NodeOrder;
H A DHexagonCommonGEP.cpp153 NodeOrdering NodeOrder; // Node ordering, for deterministic behavior. member in class:__anon2223::HexagonCommonGEP
378 NodeOrder.insert(N);
393 NodeOrder.insert(Nx);
602 GepNode *Min = *std::min_element(S.begin(), S.end(), NodeOrder);
1290 NodeOrder.clear();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.h37 NodeOrder enumerator in enum:llvm::SIScheduleCandReason
H A DSIMachineScheduler.cpp150 case NodeOrder: return "ORDER";
214 TryCand.Reason = NodeOrder;
258 TryCand.Reason = NodeOrder;
1563 TryCand.Reason = NodeOrder;
1588 TryCand.Reason = NodeOrder;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h801 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
H A DMachinePipeliner.h142 SetVector<SUnit *> NodeOrder; member in class:llvm::SwingSchedulerDAG

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