Searched refs:NextVA (Results 1 - 8 of 8) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp148 CCValAssign NextVA = VAs[1]; variable
149 assert(NextVA.needsCustom() && "Value doesn't need custom handling");
150 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
152 assert(VA.getValNo() == NextVA.getValNo() &&
156 assert(NextVA.isRegLoc() && "Value should be in reg");
167 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
372 CCValAssign NextVA = VAs[1];
373 assert(NextVA.needsCustom() && "Value doesn't need custom handling");
374 assert(NextVA
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H A DARMISelLowering.h665 CCValAssign &VA, CCValAssign &NextVA,
669 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
H A DARMFastISel.cpp2002 CCValAssign &NextVA = ArgLocs[++i]; local
2004 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2009 .addReg(NextVA.getLocReg(), RegState::Define)
2012 RegArgs.push_back(NextVA.getLocReg());
H A DARMISelLowering.cpp2059 CCValAssign &VA, CCValAssign &NextVA,
2068 if (NextVA.isRegLoc())
2069 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2071 assert(NextVA.isMemLoc());
2077 dl, DAG, NextVA,
3868 CCValAssign &NextVA,
3886 if (NextVA.isMemLoc()) {
3888 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3896 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2056 PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
3867 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &dl) const argument
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/AST/
H A DStmtIterator.h71 void NextVA();
94 NextVA();
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/
H A DStmtIterator.cpp37 void StmtIteratorBase::NextVA() { function in class:StmtIteratorBase
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp425 CCValAssign &NextVA = ArgLocs[++i]; local
428 if (NextVA.isMemLoc()) {
430 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
434 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
871 CCValAssign &NextVA = ArgLocs[++i]; local
872 if (NextVA.isRegLoc()) {
873 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
876 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2615 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
2619 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2634 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi));
2897 /// \param NextVA The next 32 bit value that need to be assigned.
2904 static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, argument
2912 assert(NextVA.getValVT() == VA.getValVT() &&
2914 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2929 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2938 DAG.getCopyFromReg(Root, Dl, NextVA.getLocReg(), MVT::i32, *InFlag);
2612 Passv64i1ArgInRegs( const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg, SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) argument
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