Searched refs:NewVec (Results 1 - 6 of 6) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 224 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, local
233 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
237 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
392 SDValue NewVec = DAG.getBuildVector(NewVecVT, dl, NewElts); local
395 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
420 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, local
430 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
434 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, H
[all...] |
| H A D | LegalizeDAG.cpp | 4606 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4607 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4645 SDValue NewVec = CastVec;
4653 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4654 NewVec, Elt, InEltIdx);
4657 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
|
| H A D | LegalizeVectorTypes.cpp | 3529 SDValue NewVec;
3539 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
3541 NewVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewInVT, InOp);
3543 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5290 SDValue NewVec = DAG.getBuildVector(AdjVT, DL, BVElts); local
5292 PreTFCRes = adjustLoadValueTypeImpl(NewVec, ReqRetVT, DL, DAG, Unpacked);
5294 PreTFCRes = NewVec;
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 7937 SDValue NewVec = DAG.getBuildVector(MVT::v4i32, dl, Parts); local
7938 return DAG.getBitcast(VT, NewVec);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | [all...] |
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