Searched refs:MRI (Results 1 - 25 of 513) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
40 MachineRegisterInfo &MRI,
43 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
[all...]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
78 MachineRegisterInfo &MRI, int RSrcIdx) const;
82 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
97 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
103 const MachineRegisterInfo &MRI,
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H A DAMDGPUGlobalISelUtils.h24 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg);
H A DAMDGPURegisterBankInfo.cpp45 MachineRegisterInfo &MRI; member in class:__anon2084::final
52 : RBI(RBI_), MRI(MRI_), NewBank(RB) {}
69 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI);
72 assert(MRI.getType(SrcReg) == LLT::scalar(1));
73 assert(MRI.getType(DstReg) == S32);
82 MRI.setRegBank(True.getReg(0), *NewBank);
83 MRI.setRegBank(False.getReg(0), *NewBank);
87 assert(!MRI.getRegClassOrRegBank(DstReg));
88 MRI.setRegBank(DstReg, *NewBank);
95 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RB
239 addMappingFromTable( const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array<unsigned, NumOps> RegSrcOpIdx, ArrayRef<OpRegBankEntry<NumOps>> Table) const argument
421 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
681 MachineRegisterInfo *MRI = B.getMRI(); local
698 setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs, LLT NewTy) argument
1035 collectWaterfallOperands( SmallSet<Register, 4> &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef<unsigned> OpIndices) const argument
1050 executeInWaterfallLoop( MachineIRBuilder &B, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef<unsigned> OpIndices) const argument
1065 executeInWaterfallLoop( MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef<unsigned> OpIndices) const argument
1073 constrainOpWithReadfirstlane( MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const argument
1101 getOtherVRegDef(const MachineRegisterInfo &MRI, Register Reg, const MachineInstr &MI) argument
1186 applyMappingImage( MachineInstr &MI, const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper, MachineRegisterInfo &MRI, int RsrcIdx) const argument
1258 handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const argument
1283 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) argument
1340 isZero(Register Reg, MachineRegisterInfo &MRI) argument
1360 MachineRegisterInfo &MRI = *B.getMRI(); local
1437 MachineRegisterInfo &MRI = *B.getMRI(); local
1472 MachineRegisterInfo &MRI = OpdMapper.getMRI(); local
2227 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
2243 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
2257 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
2293 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
2310 getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const argument
2352 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
2389 getRegBankID(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, unsigned Default) const argument
2420 getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const argument
2431 getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const argument
2439 getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const argument
2455 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
[all...]
H A DGCNRegPressure.cpp38 const MachineRegisterInfo &MRI) {
42 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
52 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
86 const MachineRegisterInfo &MRI) {
88 const auto RC = MRI.getRegClass(Reg);
89 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
100 const MachineRegisterInfo &MRI) {
110 const auto MaxMask = MRI.getMaxLaneMaskForVReg(Reg);
112 switch (auto Kind = getRegKind(Reg, MRI)) {
131 Value[Kind] += Sign * MRI
36 printLivesAt(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI) argument
85 getRegKind(unsigned Reg, const MachineRegisterInfo &MRI) argument
97 inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp52 MachineRegisterInfo &MRI) {
54 return RC->hasSubClassEq(MRI.getRegClass(Reg));
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { argument
63 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { argument
67 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { argument
71 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI);
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { argument
75 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI);
51 IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, MachineRegisterInfo &MRI) argument
78 IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) argument
86 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackendDarwin.h18 const MCRegisterInfo &MRI; member in class:llvm::ARMAsmBackendDarwin
22 const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st)
23 : ARMAsmBackend(T, STI, support::little), MRI(MRI), Subtype(st) {}
21 ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st) argument
/freebsd-11-stable/contrib/binutils/ld/
H A Dldlex.l82 MRI in an MRI script
117 %s MRI
147 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
153 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) {
178 <SCRIPT,DEFSYMEXP,MRI,BOTH,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? {
207 <BOTH,SCRIPT,EXPRESSION,MRI>"]" { RTOKEN(']');}
208 <BOTH,SCRIPT,EXPRESSION,MRI>"[" { RTOKEN('[');}
209 <BOTH,SCRIPT,EXPRESSION,MRI>"<<=" { RTOKEN(LSHIFTEQ);}
210 <BOTH,SCRIPT,EXPRESSION,MRI>">>
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.h28 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
32 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h45 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
59 MachineRegisterInfo &MRI,
77 MachineRegisterInfo &MRI,
98 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
114 const MachineRegisterInfo &MRI);
129 getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI,
133 const MachineRegisterInfo &MRI);
139 const MachineRegisterInfo &MRI);
145 const MachineRegisterInfo &MRI);
156 const MachineRegisterInfo &MRI);
167 isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) argument
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H A DMIPatternMatch.h24 bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) { argument
25 return P.match(MRI, R);
33 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { argument
34 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg);
46 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { argument
47 if (auto MaybeCst = getConstantVRegVal(Reg, MRI)) {
63 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { return true; } argument
64 bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) { argument
74 bool match(const MachineRegisterInfo &MRI, MatchSr argument
86 match(const MachineRegisterInfo &MRI, MatchSrc &&src) argument
93 match(const MachineRegisterInfo &MRI, MatchSrc &&src) argument
104 match(const MachineRegisterInfo &MRI, MatchSrc &&src) argument
118 bind(const MachineRegisterInfo &MRI, BindTy &VR, BindTy &V) argument
125 bind(const MachineRegisterInfo &MRI, MachineInstr *&MI, unsigned Reg) argument
135 bind(const MachineRegisterInfo &MRI, LLT &Ty, unsigned Reg) argument
144 bind(const MachineRegisterInfo &MRI, const ConstantFP *&F, unsigned Reg) argument
158 match(const MachineRegisterInfo &MRI, ITy &&V) argument
179 match(const MachineRegisterInfo &MRI, OpTy &&Op) argument
247 match(const MachineRegisterInfo &MRI, OpTy &&Op) argument
328 match(const MachineRegisterInfo &MRI, unsigned Reg) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LegalizerInfo.h30 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
34 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
38 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
40 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
43 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in class:__anon2017::AArch64AdvSIMDScalar
105 const MachineRegisterInfo *MRI) {
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
114 const MachineRegisterInfo *MRI) {
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
128 const MachineRegisterInfo *MRI,
145 MRI) &&
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
149 MRI)
104 isGPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument
113 isFPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument
127 getSrcFromCopy(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelector.cpp42 MachineRegisterInfo &MRI = MF.getRegInfo(); local
44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC,
50 const MachineRegisterInfo &MRI) const {
52 if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI))
58 const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
62 MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
67 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
H A DUtils.cpp30 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, argument
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
35 return MRI.createVirtualRegister(&RegClass);
42 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
72 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
119 MachineRegisterInfo &MRI = MF.getRegInfo(); local
144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TI
40 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx) argument
70 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx) argument
158 isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI) argument
207 getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI) argument
218 getConstantVRegValWithLookThrough( unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, bool HandleFConstant) argument
295 getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI) argument
303 getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) argument
319 getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI) argument
338 ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI) argument
389 isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, bool SNaN) argument
414 ConstantFoldExtOp(unsigned Opcode, const unsigned Op1, uint64_t Imm, const MachineRegisterInfo &MRI) argument
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H A DGISelChangeObserver.cpp19 const MachineRegisterInfo &MRI, unsigned Reg) {
20 for (auto &ChangingMI : MRI.use_instructions(Reg)) {
18 changingAllUsesOfReg( const MachineRegisterInfo &MRI, unsigned Reg) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCTargetDesc.h37 const MCRegisterInfo &MRI,
40 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
47 const MCRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyReplacePhysRegs.cpp69 MachineRegisterInfo &MRI = MF.getRegInfo(); local
76 MRI.leaveSSA();
77 MRI.invalidateLiveness();
88 for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E;) {
92 VReg = MRI.createVirtualRegister(RC);
H A DWebAssemblyRegColoring.cpp65 static float computeWeight(const MachineRegisterInfo *MRI, argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
88 MachineRegisterInfo *MRI = &MF.getRegInfo();
95 unsigned NumVRegs = MRI->getNumVirtRegs();
105 if (MRI->use_empty(VReg))
110 LI->weight = computeWeight(MRI, MBFI, VReg);
120 llvm::sort(SortedIntervals, [MRI](LiveInterval *LHS, LiveInterval *RHS) {
121 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg))
122 return MRI
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H A DWebAssemblyPrepareForLiveIntervals.cpp65 static bool hasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) { argument
66 for (const auto &Def : MRI.def_instructions(Reg))
80 MachineRegisterInfo &MRI = MF.getRegInfo(); local
88 MRI.leaveSSA();
97 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
101 if (MRI.use_nodbg_empty(Reg))
105 if (hasArgumentDef(Reg, MRI))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp56 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
59 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
62 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
64 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
66 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
88 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, argument
97 auto Begin = MRI->use_begin(Op0.getReg()), End = MRI->use_end();
102 if (!MRI->getUniqueVRegDef(I->getReg()))
142 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, argument
156 processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg, Register &DstReg, const GlobalValue *GVal) argument
189 processDstReg(MachineRegisterInfo *MRI, Register &DstReg, Register &SrcReg, const GlobalValue *GVal, bool doSrcRegProp) argument
226 processInst(MachineRegisterInfo *MRI, MachineInstr *Inst, MachineOperand *RelocOp, const GlobalValue *GVal) argument
241 MachineRegisterInfo *MRI = &MF->getRegInfo(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.h36 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
43 const MCRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.h26 const MCRegisterInfo &MRI)
27 : MCInstPrinter(MAI, MII, MRI) {}
30 MCRegisterInfo const &MRI);
25 AVRInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp46 MachineRegisterInfo *MRI = nullptr; member in class:__anon2494::X86FixupSetCCPass
61 MRI = &MF.getRegInfo();
80 for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
105 Register ZeroReg = MRI->createVirtualRegister(RC);
106 Register InsertReg = MRI->createVirtualRegister(RC);
119 MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCTargetDesc.h35 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,

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