Searched refs:MI1 (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp285 const MachineInstr *MI1; ///< Second instruction involved in the LOH member in struct:LOHInfo
312 Info.MI1 = nullptr;
354 OpInfo.MI1 = &MI;
356 } else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) {
359 OpInfo.MI1 = &MI;
368 if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) {
371 OpInfo.MI1 = &MI;
376 OpInfo.MI1 = &MI;
412 << '\t' << MI << '\t' << *Info.MI1 << '\t'
414 AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Inf
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsSizeReduction.cpp398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { argument
401 if (!GetImm(MI1, 2, Offset1))
406 Register Reg1 = MI1->getOperand(0).getReg();
464 MachineInstr *MI1 = Arguments->MI;
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||
469 (MI1->getOpcode() == Mips::LW_MM) ||
470 (MI1->getOpcode() == Mips::LW16_MM);
472 if (!CheckXWPInstr(MI1, ReduceToLwp, Entry))
478 Register Reg1 = MI1->getOperand(1).getReg();
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp457 MachineInstr *MI1 = *I1;
495 if (MDT.dominates(MI1, MI2)) {
496 if (!interferes(MI2, MI1)) {
505 } else if (MDT.dominates(MI2, MI1)) {
506 if (!interferes(MI1, MI2)) {
509 << printMBBReference(*MI1->getParent()) << " " << *MI1);
510 MergedInstrs.insert(MI1);
516 auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(),
524 if (!interferes(MI1,
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H A DAMDGPUSubtarget.cpp779 MachineInstr &MI1 = *SUa->getInstr(); variable
780 if ((TII->isVMEM(MI1) && TII->isVMEM(MI2)) ||
781 (TII->isFLAT(MI1) && TII->isFLAT(MI2)) ||
782 (TII->isSMRD(MI1) && TII->isSMRD(MI2)) ||
783 (TII->isDS(MI1) && TII->isDS(MI2))) {
H A DSIInstrInfo.cpp401 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, argument
413 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
416 auto MO1 = *MI1.memoperands_begin();
425 const MachineFunction &MF = *MI1.getParent()->getParent();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp301 bool VLIWPacketizerList::alias(const MachineInstr &MI1, argument
304 if (MI1.memoperands_empty() || MI2.memoperands_empty())
307 for (const MachineMemOperand *Op1 : MI1.memoperands())
H A DTargetInstrInfo.cpp420 const MachineInstr &MI1,
422 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
676 MachineInstr *MI1 = nullptr; local
679 MI1 = MRI.getUniqueVRegDef(Op1.getReg());
684 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
691 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); local
697 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
699 std::swap(MI1, MI2);
705 return MI1
419 produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDFAPacketizer.h190 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
H A DTargetInstrInfo.h543 const MachineInstr &MI1,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.h134 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
H A DHexagonSubtarget.cpp146 MachineInstr &MI1 = *SU.getInstr(); local
148 bool IsStoreMI1 = MI1.mayStore();
149 bool IsLoadMI1 = MI1.mayLoad();
150 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
H A DHexagonInstrInfo.h398 bool isToBeScheduledASAP(const MachineInstr &MI1,
410 bool addLatencyToSchedule(const MachineInstr &MI1,
H A DHexagonVLIWPacketizer.cpp959 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, argument
963 if (getPredicateSense(MI1, HII) == PK_Unknown ||
968 SUnit *SU = MIToSUnit[&MI1];
1016 unsigned PReg1 = getPredicatedRegister(MI1, HII);
1021 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1022 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
H A DHexagonInstrInfo.cpp2615 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, argument
2617 if (mayBeCurLoad(MI1)) {
2619 Register DstReg = MI1.getOperand(0).getReg();
2627 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2628 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2934 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, argument
2936 if (isHVXVec(MI1) && isHVXVec(MI2))
2937 if (!isVecUsableNextPacket(MI1, MI2))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp274 /// Returns the difference between addresses' displacements of \p MI1
277 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
397 // instructions \p MI1 and \p MI2. The numbers of the first memory operands are
399 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, argument
403 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp);
H A DX86ISelLowering.h1460 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp316 MachineInstr &MI1 = *MII;
317 dbgs() << " " << MI1;
H A DARMBaseInstrInfo.cpp1742 const MachineInstr &MI1,
1755 if (MI1.getOpcode() != Opcode)
1757 if (MI0.getNumOperands() != MI1.getNumOperands())
1761 const MachineOperand &MO1 = MI1.getOperand(1);
1793 if (MI1.getOpcode() != Opcode)
1795 if (MI0.getNumOperands() != MI1.getNumOperands())
1799 Register Addr1 = MI1.getOperand(1).getReg();
1817 const MachineOperand &MO1 = MI1.getOperand(i);
1824 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1741 produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const argument
H A DARMBaseInstrInfo.h237 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,

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