/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16RegisterInfo.cpp | 125 bool IsKill = false; local 141 IsKill = true; 143 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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H A D | MipsSERegisterInfo.cpp | 200 bool IsKill = false; local 235 IsKill = true; 252 IsKill = true; 256 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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H A D | MipsSEFrameLowering.cpp | 833 bool IsKill = !IsRAAndRetAddrIsTaken; local 835 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFInstrInfo.cpp | 126 unsigned SrcReg, bool IsKill, int FI, 135 .addReg(SrcReg, getKillRegState(IsKill)) 140 .addReg(SrcReg, getKillRegState(IsKill)) 124 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 206 bool IsKill = false; local 232 IsKill = true; 235 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
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H A D | HexagonFrameLowering.cpp | 1268 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); local 1271 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI); 1272 if (IsKill) 1633 bool IsKill = MI->getOperand(2).isKill(); local 1642 .addReg(SrcR, getKillRegState(IsKill)); 1696 bool IsKill = MI->getOperand(2).isKill(); local 1711 .addReg(SrcR, getKillRegState(IsKill)) 1785 bool IsKill = MI->getOperand(2).isKill(); local 1805 .addReg(SrcLo, getKillRegState(IsKill)) 1816 .addReg(SrcHi, getKillRegState(IsKill)) 1883 bool IsKill = MI->getOperand(2).isKill(); local [all...] |
H A D | HexagonFrameLowering.h | 169 bool IsDef, bool IsKill) const;
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H A D | HexagonBlockRanges.cpp | 326 bool IsKill = Op.isKill(); local 329 if (IsKill)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.h | 57 unsigned SourceRegister, bool IsKill, int FrameIndex,
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H A D | LanaiInstrInfo.cpp | 51 unsigned SourceRegister, bool IsKill, int FrameIndex, 63 .addReg(SourceRegister, getKillRegState(IsKill)) 49 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo * ) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.h | 42 bool IsKill, int FrameIndex,
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H A D | RISCVInstrInfo.cpp | 115 unsigned SrcReg, bool IsKill, int FI, 135 .addReg(SrcReg, getKillRegState(IsKill)) 113 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.cpp | 548 bool IsKill) { 569 .addReg(Src, getKillRegState(IsKill)); 618 bool IsKill, 696 SrcDstRegState |= getKillRegState(IsKill); 699 auto MIB = spillVGPRtoAGPR(ST, MI, Index, i, SubReg, IsKill); 706 .addReg(SubReg, getKillRegState(IsKill)); 716 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) 763 bool IsKill = MI->getOperand(0).isKill(); local 785 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill); 805 .addReg(SubReg, getKillRegState(IsKill)) 543 spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill) argument 614 buildSpillLoadStore(MachineBasicBlock::iterator MI, unsigned LoadStoreOp, int Index, unsigned ValueReg, bool IsKill, unsigned ScratchRsrcReg, unsigned ScratchOffsetReg, int64_t InstOffset, MachineMemOperand *MMO, RegScavenger *RS) const argument [all...] |
H A D | SIShrinkInstructions.cpp | 251 bool IsKill = NewAddrDwords == Info->VAddrDwords; local 264 IsKill = false; 298 MI.getOperand(VAddr0Idx).setIsKill(IsKill);
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H A D | SIInstrInfo.cpp | 1656 bool IsKill = RegOp.isKill(); local 1668 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 275 unsigned Dst, unsigned Src, bool IsKill) { 278 .addReg(Src, getKillRegState(IsKill)); 274 insertCopy(const TargetInstrInfo *TII, MachineInstr &MI, unsigned Dst, unsigned Src, bool IsKill) argument
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H A D | AArch64InstrInfo.cpp | 2825 unsigned SrcReg, bool IsKill, 2837 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) 2838 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) 2821 storeRegPairToStackSlot(const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, unsigned SrcReg, bool IsKill, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.cpp | 401 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); local 405 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask; 1101 bool IsKill = LiveRegs.available(MRI, Reg); local 1102 MO.setIsKill(IsKill);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 868 bool IsKill = MO.isKill(); local 869 if (IsKill) 871 Regs.push_back(std::make_pair(Reg, IsKill));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 794 bool IsKill = MI.getOperand(1).isKill(); local 801 .addReg(Src, getKillRegState(IsKill)); 872 if (IsKill)
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