Searched refs:IsFSHL (Results 1 - 3 of 3) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1544 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); local
1552 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
1560 APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt));
1561 APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt);
1569 Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt));
1570 Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt));
1571 Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1572 Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
5953 bool IsFSHL = Node->getOpcode() == ISD::FSHL;
5969 SDValue ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL
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H A DSelectionDAGBuilder.cpp6344 bool IsFSHL = Intrinsic == Intrinsic::fshl; local
6353 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
6363 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
6370 RotateOpcode = IsFSHL ? ISD::ROTR : ISD::ROTL;
6382 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : NShAmt);
6383 SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, X, IsFSHL ? NShAmt : ShAmt);
6391 SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : InvShAmt);
6392 SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, Y, IsFSHL ? InvShAmt : ShAmt);
6404 setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or));
H A DDAGCombiner.cpp8129 bool IsFSHL = N->getOpcode() == ISD::FSHL; local
8137 return IsFSHL ? N0 : N1;
8156 return IsFSHL ? N0 : N1;
8164 DAG.getConstant(IsFSHL ? BitWidth - ShAmt : ShAmt,
8168 DAG.getConstant(IsFSHL ? ShAmt : BitWidth - ShAmt,
8178 if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits))
8180 if (IsUndefOrZero(N1) && IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits))
8188 unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR;

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