| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DFAPacketizer.h | 51 const InstrItineraryData *InstrItins; member in class:llvm::DFAPacketizer
58 DFAPacketizer(const InstrItineraryData *InstrItins, Automaton<uint64_t> a, argument
60 : InstrItins(InstrItins), A(std::move(a)), ItinActions(ItinActions) {
102 const InstrItineraryData *getInstrItins() const { return InstrItins; }
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| H A D | TargetSchedule.h | 35 InstrItineraryData InstrItins; member in class:llvm::TargetSchedModel
85 return &InstrItins;
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| H A D | ResourcePriorityQueue.h | 62 const InstrItineraryData* InstrItins; member in class:llvm::ResourcePriorityQueue
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| H A D | MachinePipeliner.h | 65 const InstrItineraryData *InstrItins; member in class:llvm::MachinePipeliner
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 44 return EnableSchedItins && !InstrItins.isEmpty();
67 STI->initInstrItins(InstrItins);
110 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
111 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
194 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
199 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
205 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
208 // Rather than directly querying InstrItins stage latency, we call a TII
210 // applicable to the InstrItins model. InstrSchedModel should model all
279 return TII->getInstrLatency(&InstrItins, *M
[all...] |
| H A D | PostRASchedulerList.cpp | 213 const InstrItineraryData *InstrItins = local
217 InstrItins, this);
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| H A D | MachinePipeliner.cpp | 906 const InstrItineraryData *InstrItins; member in struct:__anon1761::FuncUnitSorter
911 : InstrItins(TSI.getInstrItineraryData()), STI(&TSI) {}
919 if (InstrItins && !InstrItins->isEmpty()) {
921 make_range(InstrItins->beginStage(SchedClass),
922 InstrItins->endStage(SchedClass))) {
955 llvm_unreachable("Should have non-empty InstrItins or hasInstrSchedModel!");
965 if (InstrItins && !InstrItins->isEmpty()) {
967 make_range(InstrItins
[all...] |
| H A D | TwoAddressInstructionPass.cpp | 96 const InstrItineraryData *InstrItins; member in class:__anon1833::TwoAddressInstructionPass
903 if (TII->getInstrLatency(InstrItins, *MI) > 1)
1036 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
1672 InstrItins = MF->getSubtarget().getInstrItineraryData();
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.h | 50 const InstrItineraryData *InstrItins; member in class:llvm::ScheduleDAGSDNodes
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| H A D | ScheduleDAGSDNodes.cpp | 50 InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
625 if (!InstrItins || InstrItins->isEmpty()) {
639 SU->Latency += TII->getInstrLatency(InstrItins, N);
655 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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| H A D | ResourcePriorityQueue.cpp | 44 : Picker(this), InstrItins(IS->MF->getSubtarget().getInstrItineraryData()) {
313 if (Packet.size() >= InstrItins->SchedModel.IssueWidth) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.h | 92 InstrItineraryData InstrItins; member in class:llvm::HexagonSubtarget
101 return &InstrItins;
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| H A D | HexagonSubtarget.cpp | 85 InstrItins(getInstrItineraryForCPU(CPUString)) {
88 assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
357 int DLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
436 int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.h | 205 InstrItineraryData InstrItins; member in class:llvm::MipsSubtarget
389 return &InstrItins;
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| H A D | MipsSubtarget.cpp | 245 InstrItins = getInstrItineraryForCPU(CPUName);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.h | 85 InstrItineraryData InstrItins; member in class:llvm::PPCSubtarget
183 return &InstrItins;
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| H A D | PPCSubtarget.cpp | 136 InstrItins = getInstrItineraryForCPU(CPUName);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUSubtarget.h | 289 InstrItineraryData InstrItins; member in class:llvm::GCNSubtarget
447 return &InstrItins;
1233 InstrItineraryData InstrItins; member in class:llvm::final
1255 return &InstrItins;
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| H A D | AMDGPUSubtarget.cpp | 194 InstrItins(getInstrItineraryForCPU(GPU)),
546 InstrItins(getInstrItineraryForCPU(GPU)) { }
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 210 void initInstrItins(InstrItineraryData &InstrItins) const;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 314 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
315 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.h | 493 InstrItineraryData InstrItins; member in class:llvm::ARMSubtarget
831 return &InstrItins;
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| H A D | ARMSubtarget.cpp | 204 InstrItins = getInstrItineraryForCPU(CPUString);
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