| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 665 /// FSINCOS - Compute both fsin and fcos as a single operation.
666 FSINCOS, enumerator in enum:llvm::ISD::NodeType
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 200 case ISD::FSINCOS: return "fsincos";
|
| H A D | LegalizeDAG.cpp | 2269 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
3195 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3197 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3201 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3972 case ISD::FSINCOS:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 270 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
414 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
415 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
416 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
558 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
559 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
561 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
562 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
721 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
3258 case ISD::FSINCOS
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1618 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1623 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 438 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
439 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
|
| H A D | MipsSEISelLowering.cpp | 150 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 164 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1328 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1329 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1371 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1372 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1410 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
9371 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 538 setOperationAction(ISD::FSINCOS, VT, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
590 setOperationAction(ISD::FSINCOS, VT, Expand);
656 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
758 setOperationAction(ISD::FSINCOS, VT, Expand);
1951 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1952 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 459 setOperationAction(ISD::FSINCOS, VT, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 292 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
297 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 8803 case ISD::FSINCOS:
|