Searched refs:DstVT (Results 1 - 20 of 20) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h74 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
76 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
H A DRISCVISelLowering.cpp320 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
321 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() ||
322 !SrcVT.isInteger() || !DstVT.isInteger())
325 unsigned DestBits = DstVT.getSizeInBits();
343 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
344 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp280 EVT DstVT = Dst.getValueType(); local
284 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
H A DX86FastISel.cpp97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
703 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
705 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, argument
708 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1223 EVT DstVT = VA.getValVT(); local
1225 if (SrcVT != DstVT) {
1232 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
1242 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
1521 EVT DstVT = TLI.getValueType(DL, I->getType()); local
1522 if (!TLI.isTypeLegal(DstVT))
1580 EVT DstVT = TLI.getValueType(DL, I->getType()); local
2532 EVT DstVT = TLI.getValueType(DL, I->getType()); local
3645 EVT DstVT = TLI.getValueType(DL, I->getType()); local
[all...]
H A DX86ISelLowering.cpp19301 MVT DstVT = Op->getSimpleValueType(0);
19304 if (DstVT == MVT::f128)
19305 return LowerF128Call(Op, DAG, RTLIB::getUINTTOFP(SrcVT, DstVT));
19307 if (DstVT.isVector())
19313 if (Subtarget.hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
19324 return DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, {DstVT, MVT::Other},
19326 return DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Src);
19332 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
19334 if (SrcVT == MVT::i32 && X86ScalarSSEf64 && DstVT != MVT::f80)
19336 if (Subtarget.is64Bit() && SrcVT == MVT::i64 && DstVT
[all...]
H A DX86ISelDAGToDAG.cpp1038 MVT DstVT = N->getSimpleValueType(0); local
1041 if (SrcVT.isVector() || DstVT.isVector())
1049 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
1065 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT;
1073 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
1091 MVT DstVT = N->getSimpleValueType(0); local
1094 if (SrcVT.isVector() || DstVT.isVector())
1102 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
1118 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT;
1144 SDVTList VTs = CurDAG->getVTList(DstVT, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp683 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); local
685 if (!DstVT || !SrcVT)
688 unsigned DstNumElems = DstVT->getNumElements();
697 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(),
703 Type *MidTy = VectorType::get(DstVT->getElementType(), FanOut);
729 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1065 MVT DstVT; local
1067 if (!isTypeLegal(DstTy, DstVT))
1070 if (DstVT != MVT::f32 && DstVT != MVT::f64)
1091 if (DstVT == MVT::f32)
1114 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1136 if (DstVT == MVT::f32)
1190 MVT DstVT, SrcVT; local
1192 if (!isTypeLegal(DstTy, DstVT))
1195 if (DstVT !
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp631 EVT DstVT = Op.getValueType(); local
633 unsigned NumDstEltBits = DstVT.getScalarSizeInBits();
638 return DAG.getBitcast(DstVT, V);
660 return DAG.getBitcast(DstVT, V);
679 return DAG.getBitcast(DstVT, V);
6034 EVT DstVT = Node->getValueType(0);
6038 if (SrcVT != MVT::f32 || DstVT != MVT::i64)
6072 Sign = DAG.getSExtOrTrunc(Sign, dl, DstVT);
6078 R = DAG.getZExtOrTrunc(R, dl, DstVT);
6082 DAG.getNode(ISD::SHL, dl, DstVT,
[all...]
H A DFastISel.cpp1508 EVT DstVT = TLI.getValueType(DL, I->getType()); local
1510 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1511 !DstVT.isSimple())
1516 if (!TLI.isTypeLegal(DstVT))
1530 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1558 MVT DstVT = DstEVT.getSimpleVT(); local
1566 if (SrcVT == DstVT) {
1568 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1579 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1914 EVT DstVT local
[all...]
H A DLegalizeIntegerTypes.cpp4054 EVT DstVT = N->getValueType(0); local
4055 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
4061 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4174 EVT DstVT = N->getValueType(0); local
4175 RTLIB::Libcall LC = RTLIB::getUINTTOFP(Op.getValueType(), DstVT);
4181 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
H A DDAGCombiner.cpp9253 EVT DstVT = N->getValueType(0); local
9284 !DstVT.isVector() || !DstVT.isPow2VectorType() ||
9289 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI))
9297 EVT SplitDstVT = DstVT;
9307 assert(!DstVT.isScalableVector() && "Unexpected scalable vector type");
9311 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements();
9333 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp426 auto DstVT = TLI->getValueType(DL, Dst); local
432 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT))
437 if (DstVT.getSizeInBits() < SrcVT.getSizeInBits())
452 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u)
H A DAArch64ISelDAGToDAG.cpp1190 EVT DstVT = N->getValueType(0); local
1213 DstVT = MVT::i32;
1217 if (DstVT == MVT::i64)
1223 InsertTo64 = DstVT == MVT::i64;
1226 DstVT = MVT::i32;
1230 if (DstVT == MVT::i64)
1236 InsertTo64 = DstVT == MVT::i64;
1239 DstVT = MVT::i32;
1258 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT,
H A DAArch64ISelLowering.cpp12532 EVT DstVT = N->getValueType(0);
12533 SDVTList VTs = DAG.getVTList(DstVT, MVT::Other);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1541 MVT DstVT;
1543 if (!isTypeLegal(Ty, DstVT))
1575 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1586 MVT DstVT;
1588 if (!isTypeLegal(RetTy, DstVT))
1608 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
H A DARMISelLowering.h355 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
H A DARMISelLowering.cpp5659 /// When \p DstVT, the destination type of \p BC, is on the vector
5668 EVT DstVT = BC->getValueType(0); local
5676 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5686 unsigned DstNumElt = DstVT.getVectorNumElements();
5701 *DAG.getContext(), DstVT.getScalarType(),
5704 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5722 EVT DstVT = N->getValueType(0); local
5725 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5746 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5763 if (SrcVT == MVT::f16 && DstVT
16413 MVT DstVT = (Sz == 16 ? MVT::f32 : MVT::f64); local
16439 EVT DstVT = Op.getValueType(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1102 MVT DstVT, SrcVT;
1107 if (!isTypeLegal(DstTy, DstVT))
1110 if (DstVT != MVT::i32)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1162 EVT DstVT = TLI.getValueType(DL, CI->getType()); local
1165 if (SrcVT.isInteger() != DstVT.isInteger())
1170 if (SrcVT.bitsLT(DstVT)) return false;
1178 if (TLI.getTypeAction(CI->getContext(), DstVT) ==
1180 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT);
1183 if (SrcVT != DstVT)

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