Searched refs:DstReg (Results 1 - 25 of 104) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterCoalescer.h31 unsigned DstReg = 0; member in class:llvm::CoalescerPair
36 /// The sub-register index of the old DstReg in the new coalesced register.
48 /// True when DstReg and SrcReg are reversed from the original
52 /// The register class of the coalesced register, or NULL if DstReg
54 /// SrcReg and DstReg.
64 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
70 /// Swap SrcReg and DstReg. Return false if swapping is impossible
71 /// because DstReg is a physical register, or SubIdx is set.
78 /// Return true if DstReg is a physical register.
85 /// Return true if DstReg i
[all...]
H A DOptimizePHIs.cpp101 Register DstReg = MI->getOperand(0).getReg(); local
114 if (SrcReg == DstReg)
145 Register DstReg = MI->getOperand(0).getReg(); local
146 assert(Register::isVirtualRegister(DstReg) &&
157 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
H A DTwoAddressInstructionPass.cpp164 void scanUses(unsigned DstReg);
408 unsigned &SrcReg, unsigned &DstReg,
411 DstReg = 0;
413 DstReg = MI.getOperand(0).getReg();
416 DstReg = MI.getOperand(0).getReg();
422 IsDstPhys = Register::isPhysicalRegister(DstReg);
491 unsigned SrcReg, DstReg; local
494 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
502 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { argument
509 DstReg
407 isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys) argument
519 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument
773 scanUses(unsigned DstReg) argument
834 unsigned SrcReg, DstReg; local
895 unsigned DstReg; local
1080 unsigned DstReg; local
1475 Register DstReg = DstMO.getReg(); local
1743 Register DstReg = mi->getOperand(DstIdx).getReg(); local
1801 Register DstReg = MI.getOperand(0).getReg(); local
[all...]
H A DExpandPostRAPseudos.cpp83 Register DstReg = MI->getOperand(0).getReg(); local
89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
91 assert(Register::isPhysicalRegister(DstReg) &&
111 if (DstReg != InsReg) {
123 // Implicitly define DstReg for subsequent uses.
126 CopyMI->addRegisterDefined(DstReg);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h54 Register DstReg = MI.getOperand(0).getReg(); local
61 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
62 UpdatedDefs.push_back(DstReg);
74 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc});
75 UpdatedDefs.push_back(DstReg);
84 const LLT &DstTy = MRI.getType(DstReg);
88 DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits()));
89 UpdatedDefs.push_back(DstReg);
103 Register DstReg = MI.getOperand(0).getReg(); local
109 LLT DstTy = MRI.getType(DstReg);
147 Register DstReg = MI.getOperand(0).getReg(); local
174 Register DstReg = MI.getOperand(0).getReg(); local
206 Register DstReg = MI.getOperand(0).getReg(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp139 Register DstReg = Dst.getReg(); local
142 if (Register::isVirtualRegister(DstReg) &&
147 PeepholeMap[DstReg] = SrcReg;
160 Register DstReg = Dst.getReg(); local
162 PeepholeMap[DstReg] = SrcReg;
177 Register DstReg = Dst.getReg(); local
179 PeepholeDoubleRegsMap[DstReg] =
188 Register DstReg = Dst.getReg(); local
191 if (Register::isVirtualRegister(DstReg) &&
196 PeepholeMap[DstReg]
211 Register DstReg = Dst.getReg(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp138 Register DstReg = MI.getOperand(0).getReg(); local
139 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
142 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
208 Register DstReg = local
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
242 Mask = (Chan != TRI.getHWRegChan(DstReg));
243 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
244 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
264 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src
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H A DSILowerI1Copies.cpp95 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
510 Register DstReg = MI.getOperand(0).getReg();
515 if (isLaneMaskReg(DstReg) || isVreg1(DstReg))
522 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));
526 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
570 Register DstReg = MI->getOperand(0).getReg();
571 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
596 PhiRegisters.insert(DstReg);
602 for (MachineInstr &Use : MRI->use_instructions(DstReg))
[all...]
H A DAMDGPUInstructionSelector.cpp98 Register DstReg = Dst.getReg(); local
101 if (isVCC(DstReg, *MRI)) {
107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))
129 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
141 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
210 Register DstReg = MRI->createVirtualRegister(&SubRC); local
215 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
218 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
255 Register DstReg local
296 Register DstReg = I.getOperand(0).getReg(); local
450 Register DstReg = I.getOperand(0).getReg(); local
487 Register DstReg = MI.getOperand(0).getReg(); local
588 Register DstReg = I.getOperand(0).getReg(); local
651 Register DstReg = I.getOperand(0).getReg(); local
[all...]
H A DSIFixSGPRCopies.cpp171 Register DstReg = Copy.getOperand(0).getReg(); local
181 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg)
182 ? MRI.getRegClass(DstReg)
183 : TRI.getPhysRegClass(DstReg);
207 Register DstReg = MI.getOperand(0).getReg(); local
210 !Register::isVirtualRegister(DstReg))
213 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {
223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
246 Register DstReg local
[all...]
H A DR600InstrInfo.h269 unsigned DstReg,
276 unsigned DstReg) const;
280 unsigned DstReg,
285 unsigned DstReg, unsigned SrcReg) const;
H A DAMDGPUCallLowering.h30 unsigned Align, Register DstReg) const;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp57 MachineInstr &MI, Register &SrcReg, Register &DstReg,
59 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
158 Register &DstReg, const GlobalValue *GVal) {
159 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) {
166 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end();
176 processDstReg(MRI, TmpReg, DstReg, GVal, false);
180 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
185 // All uses of DstReg replaced by SrcReg
186 processDstReg(MRI, DstReg, SrcReg, GVal, true);
190 Register &DstReg, Registe
156 processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg, Register &DstReg, const GlobalValue *GVal) argument
189 processDstReg(MachineRegisterInfo *MRI, Register &DstReg, Register &SrcReg, const GlobalValue *GVal, bool doSrcRegProp) argument
265 Register DstReg = MI.getOperand(0).getReg(); local
[all...]
H A DBPFMIPeephole.cpp187 Register DstReg = MI.getOperand(0).getReg(); local
219 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg)
414 Register DstReg, SrcReg; local
430 DstReg = MI.getOperand(0).getReg();
445 DstReg = MI.getOperand(0).getReg();
486 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::MOV_rr), DstReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; local
202 DstReg = MCI.getOperand(0).getReg();
206 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) {
220 DstReg = MCI.getOperand(0).getReg();
222 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
241 DstReg = MCI.getOperand(0).getReg();
243 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
251 DstReg = MCI.getOperand(0).getReg();
253 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
261 DstReg
542 unsigned DstReg, SrcReg; local
[all...]
H A DHexagonMCCompound.cpp80 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local
96 DstReg = MI.getOperand(0).getReg();
99 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
110 DstReg = MI.getOperand(0).getReg();
112 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
122 DstReg = MI.getOperand(0).getReg();
124 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) &&
132 DstReg
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp69 unsigned DstReg) {
70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
145 Register DstReg = MI.getOperand(0).getReg();
152 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
178 Register DstReg = MI.getOperand(0).getReg(); local
185 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
225 Register DstReg = MI.getOperand(0).getReg(); local
232 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
277 unsigned DstReg = MI.getOperand(0).getReg(); local
281 TRI->splitReg(DstReg, DstLoRe
68 buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode, unsigned DstReg) argument
329 unsigned DstReg = MI.getOperand(0).getReg(); local
392 unsigned DstReg = MI.getOperand(0).getReg(); local
422 unsigned DstReg = MI.getOperand(0).getReg(); local
455 unsigned DstReg = MI.getOperand(0).getReg(); local
490 unsigned DstReg = MI.getOperand(0).getReg(); local
539 unsigned DstReg = MI.getOperand(0).getReg(); local
583 unsigned DstReg = MI.getOperand(0).getReg(); local
632 unsigned DstReg = MI.getOperand(0).getReg(); local
663 unsigned DstReg = MI.getOperand(0).getReg(); local
694 unsigned DstReg = MI.getOperand(0).getReg(); local
749 unsigned DstReg = MI.getOperand(0).getReg(); local
1018 unsigned DstReg = MI.getOperand(0).getReg(); local
1046 unsigned DstReg = MI.getOperand(0).getReg(); local
1080 unsigned DstReg = MI.getOperand(0).getReg(); local
1114 unsigned DstReg = MI.getOperand(0).getReg(); local
1149 unsigned DstReg = MI.getOperand(0).getReg(); local
1234 unsigned DstReg = MI.getOperand(0).getReg(); local
1257 unsigned DstReg = MI.getOperand(0).getReg(); local
1294 unsigned DstReg = MI.getOperand(0).getReg(); local
1338 unsigned DstReg = MI.getOperand(0).getReg(); local
1371 unsigned DstReg = MI.getOperand(0).getReg(); local
1414 unsigned DstReg = MI.getOperand(0).getReg(); local
1457 unsigned DstReg = MI.getOperand(0).getReg(); local
1511 unsigned DstReg = MI.getOperand(0).getReg(); local
1540 unsigned DstReg = MI.getOperand(0).getReg(); local
[all...]
H A DAVRRegisterInfo.cpp98 static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, unsigned DstReg) { argument
107 // Check that DstReg matches with next instruction, otherwise the instruction
109 if (DstReg != MI.getOperand(0).getReg()) {
161 Register DstReg = MI.getOperand(0).getReg(); local
162 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
175 foldFrameOffset(II, Offset, DstReg);
177 // Select the best opcode based on DstReg and the offset size.
178 switch (DstReg) {
196 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
197 .addReg(DstReg, RegStat
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp186 MCPhysReg DstReg = PredI.getOperand(0).getReg();
195 SrcReg != DstReg) {
209 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
214 if (!DomBBClobberedRegs.available(DstReg))
218 KnownRegs.push_back(RegImm(DstReg, 0));
252 MCPhysReg DstReg = PredI.getOperand(0).getReg(); local
253 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
258 if (!DomBBClobberedRegs.available(DstReg))
[all...]
H A DAArch64ExpandPseudoInsts.cpp112 Register DstReg = MI.getOperand(0).getReg(); local
117 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
148 .addReg(DstReg, RegState::Define |
156 Register DstReg = MI.getOperand(0).getReg(); local
159 .addReg(DstReg,
163 .addReg(DstReg)
482 Register DstReg = MI.getOperand(0).getReg(); local
489 TII->get(AArch64::LDRXl), DstReg);
505 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
517 unsigned DstReg = MI.getOperand(0).getReg(); local
555 Register DstReg = MI.getOperand(0).getReg(); local
599 Register DstReg = MI.getOperand(0).getReg(); local
[all...]
H A DAArch64InstructionSelector.cpp104 /// Emit a lane insert into \p DstReg, or a new vector register if None is
110 MachineInstr *emitLaneInsert(Optional<Register> DstReg, Register SrcReg,
151 MachineInstr *emitExtractVectorElt(Optional<Register> DstReg,
587 const Register DstReg = I.getOperand(0).getReg(); local
589 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
648 Register DstReg = I.getOperand(0).getReg(); local
650 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
652 unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
674 Register DstReg = I.getOperand(0).getReg(); local
676 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MR
1100 Register DstReg = I.getOperand(0).getReg(); local
1138 Register DstReg = I.getOperand(0).getReg(); local
1243 Register DstReg = BuildMovK(MovZ.getReg(0), local
1545 Register DstReg = I.getOperand(0).getReg(); local
1676 Register DstReg = I.getOperand(0).getReg(); local
1902 Register DstReg = I.getOperand(0).getReg(); local
2042 const Register DstReg = I.getOperand(0).getReg(); local
2110 const Register DstReg = I.getOperand(0).getReg(); local
2378 const Register DstReg = I.getOperand(0).getReg(); local
2453 Register DstReg = I.getOperand(0).getReg(); local
2608 Register DstReg = I.getOperand(0).getReg(); local
2821 Register DstReg = I.getOperand(0).getReg(); local
2900 emitExtractVectorElt( Optional<Register> DstReg, const RegisterBank &DstRB, LLT ScalarTy, Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const argument
2964 Register DstReg = I.getOperand(0).getReg(); local
4028 Register DstReg = I.getOperand(0).getReg(); local
4095 Register DstReg = I.getOperand(0).getReg(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp142 Register DstReg = MI.getOperand(0).getReg();
144 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
145 .addReg(DstReg).addImm(-Offset);
147 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
148 .addReg(DstReg).addImm(Offset);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp108 const unsigned DstReg,
121 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
124 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
233 Register DstReg = I.getOperand(0).getReg(); local
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
241 if (Register::isPhysicalRegister(DstReg)) {
249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg);
278 getRegClass(MRI.getType(DstReg), DstRegBank);
296 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
690 selectTurnIntoCOPY( MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg, const TargetRegisterClass *DstRC, const unsigned SrcReg, const TargetRegisterClass *SrcRC) const argument
712 const Register DstReg = I.getOperand(0).getReg(); local
776 const Register DstReg = I.getOperand(0).getReg(); local
887 const Register DstReg = I.getOperand(0).getReg(); local
1084 const Register DstReg = I.getOperand(0).getReg(); local
1144 const Register DstReg = I.getOperand(0).getReg(); local
1195 emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1233 emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1276 const Register DstReg = I.getOperand(0).getReg(); local
1361 Register DstReg = I.getOperand(0).getReg(); local
1435 const Register DstReg = I.getOperand(0).getReg(); local
1496 Register DstReg = I.getOperand(0).getReg(); local
1527 const Register DstReg = I.getOperand(0).getReg(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp195 void LegalizerHelper::insertParts(Register DstReg, argument
204 MIRBuilder.buildMerge(DstReg, PartRegs);
209 MIRBuilder.buildConcatVectors(DstReg, PartRegs);
211 MIRBuilder.buildBuildVector(DstReg, PartRegs);
232 DstReg : MRI.createGenericVirtualRegister(ResultTy);
620 Register DstReg = MI.getOperand(0).getReg(); local
621 if(MRI.getType(DstReg).isVector())
622 MIRBuilder.buildBuildVector(DstReg, DstRegs);
624 MIRBuilder.buildMerge(DstReg, DstRegs);
733 Register DstReg local
746 Register DstReg = MI.getOperand(0).getReg(); local
766 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); local
795 Register DstReg = MI.getOperand(0).getReg(); local
814 Register DstReg = MI.getOperand(0).getReg(); local
1073 Register DstReg = MI.getOperand(0).getReg(); local
1340 Register DstReg = MI.getOperand(0).getReg(); local
1514 Register DstReg = MI.getOperand(0).getReg(); local
1540 Register DstReg = MI.getOperand(0).getReg(); local
2074 Register DstReg = MI.getOperand(0).getReg(); local
2297 Register DstReg = MI.getOperand(0).getReg(); local
2330 Register DstReg = MI.getOperand(0).getReg(); local
2359 const Register DstReg = MI.getOperand(0).getReg(); local
2423 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); local
2468 const Register DstReg = MI.getOperand(0).getReg(); local
2573 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); local
2594 Register DstReg = MI.getOperand(0).getReg(); local
2637 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); local
2661 Register DstReg = MI.getOperand(0).getReg(); local
2715 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); local
2733 const Register DstReg = MI.getOperand(0).getReg(); local
3183 Register DstReg = MI.getOperand(0).getReg(); local
3463 Register DstReg = MI.getOperand(0).getReg(); local
3552 Register DstReg = MI.getOperand(0).getReg(); local
3621 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); local
3627 Register DstReg = MI.getOperand(0).getReg(); local
3639 Register DstReg = MI.getOperand(0).getReg(); local
4125 Register DstReg = MI.getOperand(0).getReg(); local
4138 Register DstReg = MI.getOperand(0).getReg(); local
4198 Register DstReg = MI.getOperand(0).getReg(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h37 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
47 MachineBasicBlock::iterator MBBI, unsigned DstReg,
51 // Materializes the given integer Val into DstReg.
53 const DebugLoc &DL, Register DstReg, uint64_t Val,

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