Searched refs:Defs (Results 1 - 25 of 65) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/clang/utils/TableGen/
H A DClangDataCollectorsEmitter.cpp8 const auto &Defs = RK.getClasses(); local
9 for (const auto &Entry : Defs) {
H A DNeonEmitter.cpp540 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
542 SmallVectorImpl<Intrinsic *> &Defs);
544 SmallVectorImpl<Intrinsic *> &Defs);
1940 SmallVectorImpl<Intrinsic *> &Defs) {
1947 for (auto *Def : Defs) {
1967 SmallVectorImpl<Intrinsic *> &Defs) {
1981 for (auto *Def : Defs) {
2046 SmallVectorImpl<Intrinsic *> &Defs) {
2051 for (auto *Def : Defs) {
2132 SmallVector<Intrinsic *, 128> Defs;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, argument
106 InsertUsesDefs(LocalDefs, Defs);
138 RegisterSet &Defs, RegisterSet &Uses) {
152 if (Uses.count(DstReg) || Defs.count(SrcReg))
196 RegisterSet Defs, Uses; local
209 Defs.clear();
211 TrackDefUses(MI, Defs, Uses, TRI);
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
262 TrackDefUses(NMI, Defs, Use
136 MoveCopyOutOfITBlock(MachineInstr *MI, ARMCC::CondCodes CC, ARMCC::CondCodes OCC, RegisterSet &Defs, RegisterSet &Uses) argument
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H A DA15SDOptimizer.cpp401 SmallVector<unsigned, 8> Defs;
410 Defs.push_back(MO.getReg());
412 return Defs;
594 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); local
597 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCTagsEmitter.cpp66 const auto &Defs = Records.getDefs(); local
69 Tags.reserve(Classes.size() + Defs.size());
72 for (const auto &D : Defs)
H A DGICombinerEmitter.cpp351 DagInit *Defs = TheDef.getValueAsDag("Defs"); local
353 if (Defs->getOperatorAsDef(TheDef.getLoc())->getName() != "defs") {
358 for (unsigned I = 0, E = Defs->getNumArgs(); I < E; ++I) {
360 if (isSpecificDef(*Defs->getArg(I), "root")) {
361 Roots.emplace_back(Defs->getArgNameStr(I));
369 getDefOfSubClass(*Defs->getArg(I), "GIDefMatchData")) {
370 declareMatchData(Defs->getArgNameStr(I),
377 if (getDefOfSubClass(*Defs->getArg(I), "GIDefKind"))
380 else if (getDefOfSubClass(*Defs
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp73 SmallPtrSet<Value *, 8> Defs; local
76 Defs.insert(V);
85 if (Defs.insert(Op).second)
88 return Defs;
220 auto Defs = findAllDefs(U); local
223 if (llvm::none_of(Defs, isa<Instruction, Value *>))
229 for (Value *V : Defs)
234 for (Value *V : Defs)
245 for (Value *V : Defs)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; member in struct:__anon2248::HexagonGenMux::DefUseInfo
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, argument
165 expandReg(*R++, Defs);
175 BitVector &Set = MO.isDef() ? Defs : Uses;
184 BitVector Defs(NR), Uses(NR);
189 Defs.reset();
191 getDefsUses(MI, Defs, Uses);
192 DUM.insert(std::make_pair(Index, DefUseInfo(Defs, Use
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H A DHexagonRDFOpt.cpp256 NodeList Defs; local
261 Defs = DFG.getRelatedRefs(IA, DA);
262 if (!llvm::all_of(Defs, IsDead))
267 // Mark all nodes in Defs for removal.
268 for (auto D : Defs)
H A DHexagonExpandCondsets.cpp222 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
391 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs,
393 for (MachineBasicBlock *D : Defs)
401 if (Defs.count(B))
414 SetVector<MachineBasicBlock*> Defs; local
420 Defs.insert(DefI->getParent());
455 if (Dominate(Defs, BB))
791 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
794 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, argument
797 // "Defs" an
968 ReferenceMap Uses, Defs; local
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H A DHexagonBlockRanges.cpp313 RegisterSet Defs, Clobbers; local
334 Defs.clear();
346 Defs.insert(S);
365 if (!Defs.count(R))
369 // Defs and clobbers can overlap, e.g.
371 for (RegisterRef R : Defs)
375 for (RegisterRef S : Defs) {
376 // Defs should already be expanded into subregs.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp67 bool canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
69 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
70 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
209 RegUse &Defs, RegUse &Uses) const {
226 RegUse &Map = MO.isDef() ? Uses : Defs;
265 RegUse &Defs, RegUse &Uses) const {
276 RegUse &Map = MO.isDef() ? Defs : Uses;
293 RegUse &Defs, RegUse &Uses,
295 if (!canBundle(MI, Defs, Uses))
301 collectRegUses(MI, Defs, Use
208 canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const argument
264 collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const argument
292 processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses, GCNDownwardRPTracker &RPT) argument
337 RegUse Defs, Uses; local
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H A DSIFixSGPRCopies.cpp454 auto &Defs = Init.second;
456 for (auto I1 = Defs.begin(), E = Defs.end(); I1 != E; ) {
546 auto &Defs = Init.second;
547 auto I = Defs.begin();
548 while (I != Defs.end()) {
551 I = Defs.erase(I);
559 auto &Defs = Init.second;
560 for (auto MI : Defs) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp153 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); local
156 if (Defs) {
161 if (Iter != Defs->rend())
169 // Note that if MA comes before Defs->begin(), we won't hit a def.
180 auto *Defs = MSSA->getWritableBlockDefs(BB); local
182 if (Defs) {
183 CachedPreviousDef.insert({BB, &*Defs->rbegin()});
184 return &*Defs->rbegin();
261 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); local
262 (void)Defs;
460 auto *Defs = MSSA->getWritableBlockDefs(NewDef->getBlock()); local
1201 auto *Defs = MSSA->getWritableBlockDefs(From); local
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveVariables.h159 SmallVectorImpl<unsigned> &Defs);
160 void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
178 void runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
H A DRDFLiveness.h78 NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs);
141 NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs,
H A DLiveRangeCalc.h285 /// in @p Defs. This function is mainly for use in self-verification
289 ArrayRef<SlotIndex> Defs,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) {
483 Defs.push_back(Reg); // Remember this def.
487 SmallVectorImpl<unsigned> &Defs) {
488 while (!Defs.empty()) {
489 unsigned Reg = Defs.back();
490 Defs.pop_back();
501 SmallVectorImpl<unsigned> &Defs) {
559 HandlePhysRegDef(MOReg, &MI, Defs);
561 UpdatePhysRegDefs(MI, Defs);
566 SmallVector<unsigned, 4> Defs; local
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) argument
486 UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs) argument
500 runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs) argument
768 DenseSet<unsigned> Defs, Kills; local
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H A DMachineInstrBundle.cpp147 SmallVector<MachineOperand*, 4> Defs; local
154 Defs.push_back(&MO);
179 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
180 MachineOperand &MO = *Defs[i];
207 Defs.clear();
H A DRegisterPressure.cpp485 for (const RegisterMaskPair &P : RegOpers.Defs)
494 for (const RegisterMaskPair &P : RegOpers.Defs)
516 pushReg(Reg, RegOpers.Defs);
548 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs);
582 for (auto RI = Defs.begin(); RI != Defs.end(); /*empty*/) {
591 RI = Defs.erase(RI);
603 for (auto I = Defs.begin(); I != Defs.end(); ) {
615 I = Defs
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/
H A DCompileOnDemandLayer.cpp244 IRMaterializationUnit::SymbolNameToDefinitionMap Defs) {
254 assert(Defs.count(Name) && "No definition for symbol");
255 RequestedGVs.insert(Defs[Name]);
267 Defs.clear();
275 std::move(TSM), R.getSymbols(), std::move(Defs), *this));
242 emitPartition( MaterializationResponsibility R, ThreadSafeModule TSM, IRMaterializationUnit::SymbolNameToDefinitionMap Defs) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp115 /// This function sets all caller-saved registers in Defs.
118 /// This function sets all unallocatable registers in Defs.
136 BitVector Defs, Uses; member in class:__anon2321::RegDefsUses
192 /// Update Defs and Uses. Return true if there exist dependences that
194 /// Defs.
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in class:__anon2321::MemDefsUses
346 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
352 // If MI is a call, add RA to Defs to prevent users of RA from going into
355 Defs.set(Mips::RA);
361 Defs
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
45 Defs[Hexagon::LC0].insert(Unconditional);
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
49 Defs[Hexagon::LC1].insert(Unconditional);
124 Defs[R].insert(PredSense(PredReg, isTrue));
176 Defs[*SRI].insert(PredSense(PredReg, isTrue));
384 if (!Defs.count(P) || LatePreds.count(P)) {
397 if (LatePreds.count(P) > 1 || Defs.count(P)) {
496 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); local
497 for (unsigned j = 0; j < Defs;
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H A DHexagonMCChecker.h49 DenseMap<unsigned, PredSet> Defs;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h405 SmallVector<WriteState, 4> Defs; member in class:llvm::mca::InstructionBase
414 SmallVectorImpl<WriteState> &getDefs() { return Defs; }
415 const ArrayRef<WriteState> getDefs() const { return Defs; }
424 return any_of(Defs,
430 for (const WriteState &Def : Defs)

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