Searched refs:DefReg (Results 1 - 25 of 29) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp253 Register DefReg = Def.getReg(); local
254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
288 Register DefReg = Def.getReg(); local
289 if (!Register::isVirtualRegister(DefReg))
291 unsigned DefRegIdx = Register::virtReg2Index(DefReg);
431 Register DefReg = Def.getReg(); local
434 if (Register::isVirtualRegister(DefReg)) {
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
473 Register DefReg = Def.getReg(); local
474 if (!Register::isVirtualRegister(DefReg))
[all...]
H A DImplicitNullChecks.cpp625 unsigned DefReg = NoRegister; local
627 DefReg = MI->getOperand(0).getReg();
638 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)
H A DTailDuplicator.cpp350 Register DefReg = MI->getOperand(0).getReg(); local
355 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
356 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg)));
362 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
363 addSSAUpdateEntry(DefReg, NewDef, PredBB);
H A DMachineSink.cpp1175 for (auto DefReg : DefedRegsInCopy) {
1177 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI);
1210 for (unsigned DefReg : DefedRegsInCopy)
1211 for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
1339 "Unexpect SrcReg or DefReg");
H A DPHIElimination.cpp173 Register DefReg = DefMI->getOperand(0).getReg(); local
174 if (MRI->use_nodbg_empty(DefReg)) {
H A DTargetInstrInfo.cpp891 Register DefReg = MI.getOperand(0).getReg();
897 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
898 MI.readsVirtualRegister(DefReg))
949 if (MO.isDef() && Reg != DefReg)
H A DLiveVariables.cpp218 Register DefReg = MO.getReg(); local
219 if (TRI->isSubRegister(Reg, DefReg)) {
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
H A DTwoAddressInstructionPass.cpp227 unsigned DefReg = 0; local
243 if (DefReg)
246 DefReg = MO.getReg();
305 if (DefReg == MOReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp382 Register DefReg = MI->getOperand(0).getReg(); local
385 if (!MRI->isReserved(DefReg) &&
389 if (KnownReg.Reg != DefReg &&
390 !TRI->isSuperRegister(DefReg, KnownReg.Reg))
H A DAArch64InstructionSelector.cpp145 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
163 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
1392 Register DefReg = I.getOperand(0).getReg();
1393 LLT Ty = MRI.getType(DefReg);
1399 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
1402 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
1429 const Register DefReg = I.getOperand(0).getReg(); local
1430 const LLT DefTy = MRI.getType(DefReg);
1433 MRI.getRegClassOrRegBank(DefReg);
1452 return RBI.constrainGenericRegister(DefReg, *DefR
1590 const Register DefReg = I.getOperand(0).getReg(); local
1923 const Register DefReg = I.getOperand(0).getReg(); local
1967 const Register DefReg = I.getOperand(0).getReg(); local
2157 const Register DefReg = I.getOperand(0).getReg(); local
2334 const Register DefReg = I.getOperand(0).getReg(); local
3241 emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS, MachineIRBuilder &MIRBuilder) const argument
3461 emitCSetForICMP(Register DefReg, unsigned Pred, MachineIRBuilder &MIRBuilder) const argument
[all...]
H A DAArch64LoadStoreOptimizer.cpp744 // a def for DefReg is reached. Returns true, iff Fn returns true for all
746 static bool forAllMIsUntilDef(MachineInstr &MI, MCPhysReg DefReg,
757 bool isDef = any_of(I->operands(), [DefReg, TRI](MachineOperand &MOP) {
759 TRI->regsOverlap(MOP.getReg(), DefReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp439 Register DefReg = MO.getReg();
440 if (!Register::isVirtualRegister(DefReg) ||
441 !MFI.isVRegStackified(DefReg))
443 assert(MRI.hasOneNonDBGUse(DefReg));
444 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg);
588 /// DefReg = INST ... // Def (to become the new Insert)
589 /// TeeReg, Reg = TEE_... DefReg
594 /// with DefReg and TeeReg stackified. This eliminates a local.get from the
611 Register DefReg = MRI.createVirtualRegister(RegClass); local
616 .addReg(DefReg, getUndefRegStat
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h369 Register DefReg = MI.getOperand(DefIdx).getReg(); local
370 Builder.buildMerge(DefReg, Regs);
371 UpdatedDefs.push_back(DefReg);
385 Register DefReg = MI.getOperand(Idx).getReg(); local
386 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc});
387 UpdatedDefs.push_back(DefReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp507 const Register DefReg = I.getOperand(0).getReg(); local
508 LLT Ty = MRI.getType(DefReg);
509 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
545 addFullAddress(MIB, AM).addUse(DefReg);
567 const Register DefReg = I.getOperand(0).getReg(); local
568 LLT Ty = MRI.getType(DefReg);
620 const Register DefReg = I.getOperand(0).getReg(); local
621 LLT Ty = MRI.getType(DefReg);
639 const Register DefReg = I.getOperand(0).getReg(); local
640 LLT Ty = MRI.getType(DefReg);
861 unsigned DefReg = SrcReg; local
1371 Register DefReg = MRI.createGenericVirtualRegister(DstTy); local
[all...]
H A DX86DomainReassignment.cpp596 Register DefReg = DefOp.getReg(); local
597 if (!Register::isVirtualRegister(DefReg)) {
601 visitRegister(C, DefReg, Domain, Worklist);
H A DX86LoadValueInjectionLoadHardening.cpp370 RegisterRef DefReg = DFG.getPRI().normalize(Def.Addr->getRegRef(DFG));
371 for (auto UseID : L.getAllReachedUses(DefReg, Def)) {
376 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) {
H A DX86SpeculativeLoadHardening.cpp2156 Register DefReg = MI.getOperand(0).getReg();
2162 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) {
2187 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) ||
2188 (IndexMO.isReg() && IndexMO.getReg() == DefReg))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp369 int DefReg = 0; local
373 DefReg = MO.getReg();
392 if (DefReg != Reg) {
407 if (DefReg!= SpReg) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp670 Register DefReg = MI->getOperand(0).getReg(); local
676 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
700 Register DefReg = DefMI->getOperand(0).getReg(); local
719 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
759 Register DefReg = MI->getOperand(0).getReg(); local
761 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp205 unsigned DefReg = findSinkableLocalRegDef(LocalMI); local
206 if (DefReg == 0)
209 sinkLocalValueMaterialization(LocalMI, DefReg, OrderMap);
220 static bool isRegUsedByPhiNodes(unsigned DefReg, argument
223 if (P.second == DefReg)
264 unsigned DefReg,
271 if (FuncInfo.RegsWithFixups.count(DefReg))
276 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);
277 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {
295 for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) {
263 sinkLocalValueMaterialization(MachineInstr &LocalMI, unsigned DefReg, InstOrderMap &OrderMap) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp215 Register DefReg = MODef.getReg(); local
216 if (!Register::isVirtualRegister(DefReg)) {
H A DARMLoadStoreOptimizer.cpp882 Register DefReg = MO.getReg(); local
884 if (is_contained(ImpDefs, DefReg))
887 if (MI->readsRegister(DefReg))
889 ImpDefs.push_back(DefReg);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h586 void sinkLocalValueMaterialization(MachineInstr &LocalMI, unsigned DefReg,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp1041 unsigned DefReg = 0;
1048 if (DefReg != 0)
1050 DefReg = R;
1052 return DefReg;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp204 for (Register DefReg : NewVRegs)
205 UnMergeBuilder.addDef(DefReg);

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