Searched refs:DefIdx (Results 1 - 25 of 42) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h178 /// instruction of itinerary class DefClass, operand index DefIdx can be
181 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument
185 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
187 if (Forwardings[FirstDefIdx + DefIdx] == 0)
195 return Forwardings[FirstDefIdx + DefIdx] ==
202 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument
207 int DefCycle = getOperandCycle(DefClass, DefIdx);
217 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
H A DMCSubtargetInfo.h170 unsigned DefIdx) const {
171 assert(DefIdx < SC->NumWriteLatencyEntries &&
172 "MachineModel does not specify a WriteResource for DefIdx");
174 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
44 DefIdx != DefEnd; ++DefIdx) {
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp158 unsigned DefIdx = 0; local
162 ++DefIdx;
164 return DefIdx;
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); local
219 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
222 STI->getWriteLatencyEntry(SCDesc, DefIdx);
238 // If DefIdx does not exist in the model (e.g. implicit defs), then return
244 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
H A DTargetInstrInfo.cpp1037 SDNode *DefNode, unsigned DefIdx,
1047 return ItinData->getOperandCycle(DefClass, DefIdx);
1049 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1111 unsigned DefIdx) const {
1117 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1189 unsigned DefIdx,
1194 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1214 const MachineInstr &MI, unsigned DefIdx,
1220 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
1224 assert(DefIdx
1036 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
1187 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
1213 getRegSequenceInputs( const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const argument
1240 getExtractSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const argument
1265 getInsertSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const argument
[all...]
H A DPeepholeOptimizer.cpp370 unsigned DefIdx = 0;
424 DefIdx = MRI.def_begin(Reg).getOperandNo();
1818 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1839 const MachineOperand DefOp = Def->getOperand(DefIdx);
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1883 if (Def->getOperand(DefIdx).getSubReg())
1906 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1927 if (Def->getOperand(DefIdx).getSubReg())
1940 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1956 const MachineOperand &MODef = Def->getOperand(DefIdx);
[all...]
H A DLiveRangeCalc.cpp67 SlotIndex DefIdx = local
71 LR.createDeadDef(DefIdx, Alloc);
199 unsigned DefIdx; local
202 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
205 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
H A DLiveRangeEdit.cpp149 SlotIndex DefIdx;
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
158 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
H A DTargetRegisterInfo.cpp352 unsigned SrcIdx, DefIdx;
355 SrcIdx, DefIdx) != nullptr;
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot();
H A DMachineInstr.cpp281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); local
282 if (DefIdx != -1)
283 tieOperands(DefIdx, OpNo);
846 unsigned DefIdx; local
847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
848 OpIdx = DefIdx;
1038 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1050 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { argument
1051 MachineOperand &DefMO = getOperand(DefIdx);
1053 assert(DefMO.isDef() && "DefIdx mus
[all...]
H A DMachineVerifier.cpp269 SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1672 unsigned DefIdx; local
1674 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1675 Reg != MI->getOperand(DefIdx).getReg())
1892 unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1894 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
1896 if (VNI->def != DefIdx) {
1903 report_context(DefIdx);
1911 report_context(DefIdx);
1915 LiveQueryResult LRQ = LR.Query(DefIdx);
1891 checkLivenessAtDef(const MachineOperand *MO, unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit, bool SubRangeCheck, LaneBitmask LaneMask) argument
2064 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h141 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter
160 return DefIdx-1;
H A DScheduleDAGSDNodes.cpp571 DefIdx = 0;
577 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
585 for (;DefIdx < NodeNumDefs; ++DefIdx) {
586 if (!Node->hasAnyUseOfValue(DefIdx))
588 ValueType = Node->getSimpleValueType(DefIdx);
589 ++DefIdx;
651 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
655 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h46 /// and \p DefIdx.
55 /// with the pair \p MI, \p DefIdx. False otherwise.
59 const MachineInstr &MI, unsigned DefIdx,
63 /// and \p DefIdx.
69 /// with the pair \p MI, \p DefIdx. False otherwise.
72 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
76 /// and \p DefIdx.
84 /// with the pair \p MI, \p DefIdx. False otherwise.
88 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
318 const MachineInstr &DefMI, unsigned DefIdx,
[all...]
H A DARMBaseInstrInfo.cpp3746 unsigned DefIdx, unsigned DefAlign) const {
3747 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3750 return ItinData->getOperandCycle(DefClass, DefIdx);
3803 unsigned DefIdx, unsigned DefAlign) const {
3804 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3807 return ItinData->getOperandCycle(DefClass, DefIdx);
3906 unsigned DefIdx, unsigned DefAlign,
3912 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3913 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3922 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3743 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3800 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3904 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
4015 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
4248 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
4284 getOperandLatencyImpl( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const argument
4345 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
4689 hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h327 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs;
328 ++j, ++DefIdx)
329 DstRegs.push_back(MI.getOperand(DefIdx).getReg());
363 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
365 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs;
369 Register DefReg = MI.getOperand(DefIdx).getReg();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
218 DefIdx != DefEnd; ++DefIdx) {
221 DefIdx);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h477 /// and \p DefIdx.
487 /// with the pair \p MI, \p DefIdx. False otherwise.
495 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
499 /// and \p DefIdx.
505 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
513 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
517 /// and \p DefIdx.
525 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
533 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1139 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx
1144 getRegSequenceLikeInputs( const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const argument
1158 getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const argument
1173 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const argument
1496 hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp620 int DefIdx = SwapMap[DefMI]; local
621 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
625 SwapVector[DefIdx].VSEId,
701 int DefIdx = SwapMap[DefMI]; local
703 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
704 SwapVector[DefIdx].IsStore) {
710 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": ");
777 int DefIdx = SwapMap[DefMI]; local
778 SwapVector[DefIdx]
[all...]
H A DPPCInstrInfo.h213 const MachineInstr &DefMI, unsigned DefIdx,
217 SDNode *DefNode, unsigned DefIdx,
219 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
225 unsigned DefIdx) const override {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp150 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); local
151 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
152 I.tieOperands(DefIdx, OpI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp204 unsigned DefIdx = 0; local
208 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
209 IsTiedToChangedOp = OpChanged[DefIdx];
295 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp536 int DefIdx = mapRegToGPRIndex(Def.getReg()); local
538 if (DefIdx >= 0 && OpIdx >= 0 &&
539 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx]))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp424 int DefIdx = -1; local
428 DefIdx = OpNum;
430 assert(DefIdx >= 0 && "Def Reg not found in Src MI");
437 DefIdx, *DstI, OpNum));

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