Searched refs:CCOp (Results 1 - 6 of 6) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 1424 SDValue CCOp; local
1426 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1438 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1179 const MachineOperand &CCOp = I.getOperand(1);
1180 Register CCReg = CCOp.getReg();
1191 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1805 ISD::CondCode CC, SDValue CCOp,
1835 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1915 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp,
1938 if (!CCOp.getNode())
1941 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
1943 CCOp = ExtraCmp;
1949 if (!CCOp)
1952 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
2013 SDValue CmpR = emitConjunctionRec(DAG, RHS, RHSCC, NegateR, CCOp, Predicate);
1804 emitConditionalComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) argument
1914 emitConjunctionRec(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 3670 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3672 if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3690 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType());
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 710 struct CCOp { struct in class:__anon2168::ARMOperand
833 struct CCOp CC;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 11060 SDValue CCOp; local
11062 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
11075 CCOp, TrueVal, FalseVal);
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