| /freebsd-11-stable/contrib/gcc/config/s390/ |
| H A D | s390.c | 474 CC1 and CC2 for mixed selected bits (TMxx), it is false
496 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
824 const int CC1 = 1 << 2; local
839 case NE: return CC1 | CC2 | CC3;
847 case EQ: return CC1;
857 case NE: return CC0 | CC1 | CC3;
866 case NE: return CC0 | CC1 | CC2;
875 case NE: return CC1 | CC3;
884 case GEU: return CC0 | CC1; /* no carry */
892 case GTU: return CC0 | CC1; /* borro
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineMulDivRem.cpp | 441 Constant *CC1 = ConstantExpr::getFMul(C, C1); local
442 if (CC1->isNormalFP())
443 return BinaryOperator::CreateFDivFMF(CC1, X, &I);
463 Constant *CC1 = ConstantExpr::getFMul(C, C1); local
465 return BinaryOperator::CreateFAddFMF(XC, CC1, &I);
469 Constant *CC1 = ConstantExpr::getFMul(C, C1); local
471 return BinaryOperator::CreateFSubFMF(CC1, XC, &I);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5067 AArch64CC::CondCode CC1, CC2; local
5068 changeFPCCToAArch64CC(CC, CC1, CC2);
5069 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
5272 AArch64CC::CondCode CC1, CC2; local
5273 changeFPCCToAArch64CC(CC, CC1, CC2);
5276 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1, local
5278 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
5291 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
5453 AArch64CC::CondCode CC1, CC2; local
5454 changeFPCCToAArch64CC(CC, CC1, CC
8508 AArch64CC::CondCode CC1, CC2; local
[all...] |
| H A D | AArch64InstructionSelector.cpp | 2319 AArch64CC::CondCode CC1, CC2;
2321 (CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
2344 .addImm(getInvertedCondCode(CC1));
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1672 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1679 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1683 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1702 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1721 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1722 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling);
1725 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1726 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling);
|
| H A D | DAGCombiner.cpp | 4555 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get(); local
4557 if (LR == RR && CC0 == CC1 && IsInteger) {
4562 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4564 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4566 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4568 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4577 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4581 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4583 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
4585 bool OrNeNeg1 = !IsAnd && CC1
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 524 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
526 if (CC1 == CC2)
529 switch (CC1) {
|
| H A D | ARMISelLowering.cpp | 4780 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local
4821 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4827 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 21415 unsigned CC0, CC1;
21419 CC1 = 0; // EQ
21424 CC1 = 4; // NEQ
21435 {Chain, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8)});
21442 Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8));
[all...] |