Searched refs:Available (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMachineScheduler.cpp11 // the MachineScheduler. It has a sorted Available set of SUs and a pickNode()
162 if (Available.empty())
166 if (Available.size() == 1) {
168 HazardRec->dumpSU(*Available.begin(), dbgs()); dbgs() << "\n";);
169 return *Available.begin();
172 // All nodes that are possible to schedule are stored in the Available set.
173 LLVM_DEBUG(dbgs() << "** Available: "; Available.dump(*HazardRec););
176 for (auto *SU : Available) {
243 if (Available
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H A DSystemZMachineScheduler.h11 // the MachineScheduler. It has a sorted Available set of SUs and a pickNode()
71 // A sorter for the Available set that makes sure that SUs are considered
96 SUSet Available; member in class:llvm::SystemZPostRASchedStrategy
146 /// Available.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp65 (Available[CurInstKind].empty());
67 (!Available[IDFetch].empty() || !Available[IDOther].empty());
69 if (CurInstKind == IDAlu && !Available[IDFetch].empty()) {
76 (FetchInstCount + Available[IDFetch].size());
86 // Available[IDFetch].size() * 2 : GPRs required in the Fetch clause
92 unsigned NearRegisterRequirement = 2 * Available[IDFetch].size();
176 MoveUnits(Pending[IDFetch], Available[IDFetch]);
204 Available[IDOther].push_back(SU);
455 std::vector<SUnit *> &AQ = Available[QI
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H A DR600MachineScheduler.h53 std::vector<SUnit *> Available[IDLast], Pending[IDLast]; member in class:llvm::final
H A DGCNSchedStrategy.cpp150 ReadyQueue &Q = Zone.Available;
272 assert(Top.Available.empty() && Top.Pending.empty() &&
273 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp358 Available.push(SU);
384 LLVM_DEBUG(dbgs() << "*** Next cycle " << Available.getName() << " cycle "
421 if (Available.empty())
439 Available.push(SU);
448 if (Available.isInQueue(SU))
449 Available.remove(Available.find(SU));
464 if (Available.empty())
466 if (Available.size() == 1 && Pending.size() > 0)
467 return !ResourceModel->isResourceAvailable(*Available
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H A DHexagonMachineScheduler.h137 ReadyQueue Available; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary
157 : Available(ID, Name+".A"),
192 return Available.getID() == ConvergingVLIWScheduler::TopQID;
/freebsd-11-stable/release/packages/
H A DMakefile.package39 hast_COMMENT= Highly Available Storage daemon
40 hast_DESC= Highly Available Storage daemon
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp378 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass); local
379 Available &= Candidates;
387 Reg = Available.find_first();
399 Available.reset(Reg);
403 SpReg = Available.find_first();
415 Available.reset(SpReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineScheduler.cpp1859 Available.clear();
2050 LLVM_DEBUG(dbgs() << Available.getName() << " RemLatency SU("
2067 LLVM_DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
2079 dbgs() << " " << Available.getName() << " + Remain CritRes: "
2105 checkHazard(SU) || (Available.size() >= ReadyListLimit);
2108 Available.push(SU);
2154 LLVM_DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName()
2304 LLVM_DEBUG(dbgs() << " " << Available.getName() << " TopLatency SU("
2309 LLVM_DEBUG(dbgs() << " " << Available.getName() << " BotLatency SU("
2351 if (Available
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H A DRegisterScavenging.cpp371 /// Given the bitvector \p Available of free register units at position
553 BitVector Available = getRegsAvailable(RC); local
554 Available &= Candidates;
555 if (Available.any())
556 Candidates = Available;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
H A DSafepointIRVerifier.cpp517 AvailableValueSet &Available);
784 AvailableValueSet &Available) {
787 Available.clear();
789 Available.insert(&I);
783 transferInstruction(const Instruction &I, bool &Cleared, AvailableValueSet &Available) argument
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/scudo/standalone/
H A Dchunk.h61 enum State : u8 { Available = 0, Allocated = 1, Quarantined = 2 };
H A Dcombined.h64 NewHeader.State = Chunk::State::Available;
110 NewHeader.State = Chunk::State::Available;
648 NewHeader.State = Chunk::State::Available;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h617 ReadyQueue Available; member in class:llvm::SchedBoundary
684 Available(ID, Name+".A"), Pending(ID << LogMaxQID, Name+".P") {
696 return Available.getID() == TopQID;
783 /// Call this before applying any other heuristics to the Available queue.
784 /// Updates the Available/Pending Q's if necessary and returns the single
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp883 BitVector Available = RS.getRegsAvailable(&AVR::GPR8RegClass); local
884 Available &= Candidates;
886 signed Reg = Available.find_first();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DScalarEvolution.cpp5179 bool Available = true;
5190 Available = false;
5245 return CA.Available;
/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaOverload.cpp10972 bool Available = checkAddressOfCandidateIsAvailable(S, Cand->Function);
10973 (void)Available;
10974 assert(!Available);
/freebsd-11-stable/contrib/sqlite3/
H A Dshell.c18078 utf8_printf(p->out, "Available file-controls:\n");
20135 utf8_printf(p->out, "Available test-controls:\n");

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